ADUCM360 AD [Analog Devices], ADUCM360 Datasheet - Page 9

• Manufacturer Part Number: ADUCM360
• Description: Low Power Precision Analog Microcontroller
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
These numbers are not production tested but are guaranteed by design and/or characterization data at production release.
Tested at gain range = 4 after initial offset calibration.
These numbers do not include internal reference temperature drift.
Measured with an internal short. A system zero-scale calibration removes this error.
A recalibration at any temperature removes these errors.
Factory calibrated at gain = 1.
System calibration at a specific gain range removes the error at this gain range.
Measured using the box method.
Input current measured with one ADC measuring a channel. If both ADCs measure the same input channel, then the input current will increase – approximately
double
common mode voltage.
Endurance is qualified to 20,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
Parameter
POWER REQUIREMENTS
Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7mA.
Total I
Reference DAC linearity is calculated using a reduced code range of 0x0AB to 0xF30.
Retention lifetime equivalent at junction temperature (T
Voltage input levels only relevant if driving XTAL input from a voltage source. If a crystal is connected directly, the internal crystal interface will determine the
From MCU Power-Down
(mode 1, 2 and 3)
From TOTAL-HALT or
HIBERNATE (mode 4 or mode
5) mode
Power Supply Voltages
Power Consumption
VDD
I
I
I
Modulator
I
External Reference Input
buffers
DD
DD
DD
DD
DD
for ADC includes figures for PGA≥32, input buffers, digital interface and the Sigma Delta modulator.
(Auxiliary ADC)
(MCU Active Mode)
(MCU Powered Down)
(Primary ADC) (total)
PGA
Input Buffers
Digital Interface +
14,15
15
1
Test Conditions/Comments
Fclk is the Cortex-M3 core clock
MCU clock rate = 16 MHz, all
peripherals on
MCU clock rate = 500 KHz, Both
ADCs on (Input buffers off ) with
PGAs Gain = 4, 1 x SPI on, all
timers on
Full temperature range
HIBERNATE (mode 5)
Reduced temperature range
−40°C to +85°C
PGA enabled – total, G>=32
G=4/8/16 – PGA only
G=32/64/128 – PGA only
2 x Input buffers is 70uA
Input buffers off, G=4/8/16 only
60uA each
J
) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
Rev. Pr R| Page 9 of 21
Min
1.8
Typ
3-5 x Fclk
30.8
5.5
1
4
2
320
130
180
70
70
200
120
ADuCM360/ADuCM361
Max
3.6
10
5
Unit
μs
V
mA
mA
μA
μA
μA
μA
μA
μA
μA
μA