ADG407 AD [Analog Devices], ADG407 Datasheet - Page 6

• Manufacturer Part Number: ADG407
• Description: LC2MOS 8-/16-Channel High Performance Analog Multiplexers
• Manufacturer: AD [Analog Devices]

ADG406/ADG407/ADG426
TIMING DIAGRAMS (ADG426)
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while WR is held low, the latches are transparent and
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of WR.
Figure 2 shows the Reset Pulse Width, t
Off Time, t
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. t
A0, A1, A2, (A3)
OUTPUT
SWITCH
WR
EN
RS
0V
3V
3V
0V
OFF
0V
3V
0V
V
0
(RS).
50%
R
Figure 1.
Figure 2.
= t
50%
2V
F
t
W
= 20 ns.
t
OFF
t
t
S
RS
(RS)
50%
RS
0.8V
50%
, and the Reset Turn
t
H
0.8V
0
–6–
TERMINOLOGY
V
V
GND
R
R
I
I
I
V
C
C
C
C
t
t
t
t
V
V
I
Crosstalk
Off Isolation
Charge
Injection
I
I
ON
OFF
TRANSITION
OPEN
S
D
D
INL
DD
SS
DD
D
INL
INH
SS
ON
ON
S
D
D
IN
(OFF)
, I
(OFF)
, C
(OFF)
(OFF)
(EN)
(V
(EN)
(I
Match
S
(ON)
INH
S
S
)
(ON)
)
A measure of unwanted signal which is
Most positive power supply potential.
Most negative power supply potential in dual
supplies. In single supply applications, it may
be connected to ground.
Ground (0 V) reference.
Ohmic resistance between D and S.
Difference between the R
channels.
Source leakage current when the switch is off.
Drain leakage current when the switch is off.
Channel leakage current when the switch
is on.
Analog voltage on terminals D, S.
Channel input capacitance for “OFF”
condition.
Channel output capacitance for “OFF”
condition.
“ON” switch capacitance.
Digital input capacitance.
Delay time between the 50% and 90%
points of the digital input and switch “ON”
condition.
Delay time between the 50% and 90%
points of the digital input and switch “OFF”
condition.
Delay time between the 50% and 90%
points of the digital inputs and the switch
“ON” condition when switching from one
address state to another.
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
Maximum input voltage for logic “0.”
Minimum input voltage for logic “1.”
Input current of the digital input.
coupled through from one channel to another
as a result of parasitic capacitance.
A measure of unwanted signal coupling
through an “OFF” channel.
A measure of the glitch impulse
transferred from the digital input to the analog
output during switching.
Positive supply current.
Negative supply current.
ON
of any two
REV. 0