ADG453 AD [Analog Devices], ADG453 Datasheet - Page 8

• Manufacturer Part Number: ADG453
• Description: LC2MOS 5 ohm RON SPST Switches
• Manufacturer: AD [Analog Devices]

ADG451/ADG452/ADG453
–2.0
–3.0
–3.5
–0.5
–1.0
–1.5
–2.5
Figure 10. Frequency Response with Switch On
120
100
0
80
60
40
20
0
1
100
Figure 9. Crosstalk vs. Frequency
1k
10k
FREQUENCY – MHz
FREQUENCY – Hz
10
100k
V
V
V
1M
DD
SS
L
=
= –15V
=
V
V
V
R
DD
SS
L
LOAD
5V
=
15V
= –15V
=
10M
5V
= 50
15V
100
100M
200
–8–
APPLICATION
Figure 11 illustrates a precise, fast, sample-and-hold circuit.
An AD845 is used as the input buffer while the output
operational amplifier is an AD711. During the track mode,
SW1 is closed and the output V
V
held by the hold capacitor C
Due to switch and capacitor leakage, the voltage on the
hold capacitor will decrease with time. The ADG451/
ADG452/ADG453 minimizes this droop due to its low
leakage specifications. The droop rate is further minimized
by the use of a polystyrene hold capacitor. The droop rate
for the circuit shown is typically 30 V/ s.
A second switch, SW2, that operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differ-
ential effect on the op amp AD711, which will minimize
charge injection effects. Pedestal error is also reduced by the
compensation network R
work reduces the hold time glitch while optimizing the ac-
quisition time. Using the illustrated op amps and component
values, the pedestal error has a maximum value of 5 mV over
the 10 V input range. Both the acquisition and settling
times are 850 ns.
V
IN
IN
Figure 11. Fast, Accurate Sample-and-Hold Circuit
. In the hold mode, SW1 is opened and the signal is
+15V
–15V
AD845
+15V
SW1
SW2
S
S
ADG451/
452/453
–15V
+5V
D
D
C
and C
H
.
75
R
C
OUT
C
. This compensation net-
C
1000pF
follows the input signal
C
CH
2200pF
2200pF
AD711
+15V
–15V
V
REV. A
OUT