HD6433308 HITACHI [Hitachi Semiconductor], HD6433308 Datasheet - Page 246

• Manufacturer Part Number: HD6433308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

(4) After the master CPU has finished writing data, the H8/300 CPU first reads PCDR14. This
(5) If the master CPU has more data to send, it should check that MWMF is cleared to "0," then
11.3.2 Data Transfer from H8/300 CPU to Master CPU
The following procedure should be used when the H8/300 CPU sends data to the master CPU via
the dual-port RAM:
(1) The H8/300 CPU writes the first byte of data in PCDR0. If the dual-port RAM is not
(2) The H8/300 CPU reads the PCCSR and checks SWMF. If SWMF is set to “1,” the H8/300
(3) The H8/300 CPU writes data in PCDR1 to PCDR13 as required, then writes the last byte in
(4) After the H8/300 CPU has finished writing data, the master CPU first reads PCDR14. This
(5) If the H8/300 CPU has more data to send, it should check that SWMF is cleared to "0," then
clears the master write end flag. Then the H8/300 CPU reads data from PCDR1 to PCDR13 as
required. Finally, the H8/300 CPU reads PCDR0. This clears MWMF, so the dual-port RAM
is no longer in the master write mode. If the EAKAR bit is set to “1,” the RDY signal goes
Low to acknowledge the received data.
repeat the above procedure from step (1). If MWMF is still set to "1," that indicates that the
H8/300 CPU has not read all the data sent previously.
currently in the master write mode, SWMF is set to "1," placing it in the slave write mode and
preventing the master CPU from writing in PCDR1 to PCDR14.
CPU may continue writing in PCDR1 to PCDR14. If SWMF is cleared to "0," the dual-port
RAM is presumably in the master write mode.
PCDR14. This sets the slave write end flag (SWEF) to “1.” If the EAKAR bit is set to “1,”
the RDY signal goes Low to notify the master CPU that the H8/300 CPU has finished writing.
clears the slave write end flag. Then the master CPU reads data from PCDR1 to PCDR13 as
required. Finally, the master CPU reads PCDR0. This clears the SWMF bit, so the dual-port
RAM is no longer in the slave write mode. It also sets the master read end flag (MREF). If
EMRI is set to “1,” a master read end interrupt is requested to notify the H8/300 CPU that the
master CPU has finished reading the data.
repeat the above procedure from step (1). If SWMF is still set to "1," that indicates that the
master CPU has not read all the data sent previously.
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