HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 363
HD64570
Manufacturer Part Number
HD64570
Description
Serial Communications Adaptor
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD64570.pdf
(469 pages)
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Table 10.7 CPU Mode 0 Master Mode Bus Timing
(V
Item
Clock cycle time
Clock high-level pulse width
Clock low-level pulse width
Clock fall time
Clock rise time
Address delay time
Address set-up time
AS active delay time
RD active delay time
Address hold time
AS inactive delay time
RD inactive delay time
Data read set-up time
Data read hold time
WAIT set-up time
WAIT inactive set-up time
WAIT hold time
Write data floating delay time
WR active delay time
Write data delay time
Write data set-up time
WR inactive delay time
WR pulse width
Write data hold time
AS high-level pulse width
AS low-level pulse width
CC
= 5 V
10%, V
SS
= 0 V, Ta = 20 to +75 C unless otherwise specified)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLCL
CHCL
CLCH
CL2CL1
CH1CH2
CLAV
AVAL
CHLL
CLRL
LLAX
CLLH
CLRH
DVCL
RDX
RYLCL
RYHCH
CHRYX
CHDX
CVCTV
CLDV
DVWL
CVCTX
WLWH
WHDX
ASWH
ASWL
Min
100
40
40
20
10
25
0
30
30
30
15
110
10
70
80
Typ
Rev. 0, 07/98, page 347 of 453
Max
2000
10
10
55
50
50
50
50
60
50
60
55
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing
Figure 10.5,
figure 10.6
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