STA559BWQS13TR STMICROELECTRONICS [STMicroelectronics], STA559BWQS13TR Datasheet - Page 32

• Manufacturer Part Number: STA559BWQS13TR
• Description: 5-V, 2-A, 2.1-channel high-efficiency digital audio system with QSound QHD
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Register description
5.2.4
5.2.5
32/66
Table 20.
Delay serial clock enable
Table 21.
Channel input mapping
Table 22.
Each channel received via I
Channel Input Mapping registers. This allows for flexibility in processing. The default
settings of these registers map each I
channel.
Bit
Bit
5
6
7
BICKI
64 fs
RW
RW
RW
RW
RW
Supported serial audio input formats for LSB-First (SAIFB = 1) (continued)
Delay serial clock enable
Channel input mapping
RST
RST
0
0
1
SAI [3:0]
0000
0100
1000
1100
0001
0101
1001
1101
0010
0110
1010
1110
2
S can be mapped to any internal processing channel via the
DSCKE
Name
Name
C1IM
C2IM
2
S input channel to its corresponding processing
SAIFB
1
1
1
1
1
1
1
1
1
1
1
1
0: Processing channel 1 receives left I
1: Processing channel 1 receives right I
0: Processing channel 2 receives left I
1: Processing channel 2 receives right I
Delay serial clock enable:
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate
anomalies in some I²S master devices
I
I
I
LSB first I
Left-Justified 24 bit data
Left-Justified 20 bit data
Left-Justified 18 bit data
Left-Justified 16 bit data
Right-Justified 24 bit data
Right-Justified 20 bit data
Right-Justified 18 bit data
Right-Justified 16 bit data
2
2
2
S 24 bit data
S 20 bit data
S 18 bit data
2
S 16 bit data
Description
Description
Interface format
STA559BWQS
2
2
S input
S input
2
2
S input
S input