LT3430EFE-1 LINER [Linear Technology], LT3430EFE-1 Datasheet - Page 24
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LT3430EFE-1
Manufacturer Part Number
LT3430EFE-1
Description
High Voltage, 3A,200kHz/100kHz Step-Down Switching Regulators
Manufacturer
LINER [Linear Technology]
Datasheet
1.LT3430EFE-1.pdf
(28 pages)
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LT3430/LT3430-1
APPLICATIONS INFORMATION
DUAL OUTPUT SEPIC CONVERTER
The circuit in Figure 14 generates both positive and negative
5V outputs with a single piece of magnetics. The two induc-
tors shown are actually just two windings on a standard
Coiltronics inductor. The topology for the 5V output is a
standard buck converter. The – 5V topology would be a
simple fl yback winding coupled to the buck converter if
C4 were not present. C4 creates a SEPIC (single-ended
primary inductance converter) topology which improves
regulation and reduces ripple current in L1. Without C4,
the voltage swing on L1B compared to L1A would vary
due to relative loading and coupling losses. C4 provides a
low impedance path to maintain an equal voltage swing in
L1B, improving regulation. In a fl yback converter, during
switch on time, all the converter’s energy is stored in L1A
only, since no current fl ows in L1B. At switch off, energy
is transferred by magnetic coupling into L1B, powering
the –5V rail. C4 pulls L1B positive during switch on time,
causing current to fl ow, and energy to build in L1B and
C4. At switch off, the energy stored in both L1B and C4
supply the –5V rail. This reduces the current in L1A and
changes L1B current waveform from square to triangular.
For details on this circuit, including maximum output cur-
rents, see Design Note 100.
24
* L1 IS A SINGLE CORE WITH TWO WINDINGS
†
7.5V TO 60V
COILTRONICS #CTX25-4A
IF LOAD CAN GO TO ZERO, AN OPTIONAL
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: 30BQ060
CERAMIC
GND
V
IN
100V
4.7µF
C3
Figure 14. Dual Output SEPIC Converter
V
SHDN
SYNC
GND
0.022µF
IN
LT3430
3.3k
C
BOOST
C
R
C
V
SW
C
FB
100µF
TANT
0.68µF
10V
C
220pF
C4
F
POSITIVE-TO-NEGATIVE CONVERTER
The circuit in Figure 15 is a positive-to-negative topology
using a grounded inductor. It differs from the standard
approach in the way the IC chip derives its feedback
signal because the LT3430/LT3430-1 accepts only posi-
tive feedback signals. The ground pin must be tied to the
regulated negative output. A resistor divider to the FB pin
then provides the proper feedback voltage for the chip.
The following equation can be used to calculate maximum
load current for the positive-to-negative converter:
V
V
V
0.15 = Switch voltage drop at 3A
Example: with V
V
C2
IN
OUT
F
F
+
I
I
= Catch diode forward voltage
= 0.52V, I
P
MAX
= Minimum input voltage
= Maximum rated switch current
= Output voltage
L1B*
MMSD914TI
=
D1
D3
⎡
⎢
⎣
25µH
D2
L1A*
I
4.99k
P
15.4k
P
R2
R1
–
= 3A: I
10V TANT
2
IN(MIN)
100µF
(
(
V
V
C5
OUT
OUT
+
(
V
MAX
+
IN
+
C1
100µF
10V TANT
)(
+
= 5.5V, V
3430 F14
= 0.6A.
V
V
V
OUT
IN
IN
V
5V
V
–5V
)( )( )
– . )(
OUT
OUT
)
f L
0 15
†
OUT
⎤
⎥
⎦
(
V
V
OUT
= 12V, L = 10µH,
OUT
)(
+
V
IN
V
F
– . )
)
0 15
34301fa