LT3493 LINER [Linear Technology], LT3493 Datasheet - Page 16

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LT3493

Manufacturer Part Number
LT3493
Description
Manufacturer
LINER [Linear Technology]
Datasheet

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LT3493
APPLICATIONS INFORMATION
model works well as long as the value of the inductor is
not too high and the loop crossover frequency is much
lower than the switching frequency. With a larger ceramic
capacitor (very low ESR), crossover may be lower and a
phase lead capacitor (C
improve the phase margin and transient response. Large
electrolytic capacitors may have an ESR large enough to
create an additional zero, and the phase lead may not be
necessary.
If the output capacitor is different than the recommended
capacitor, stability should be checked across all operating
16
100pF
LT3493
C
GND
60k
R
C
C
V
C
0.7V
1M
Figure 10. Model for Loop Response
AMPLIFIER
+
ERROR
1.6A/V
g
m
300μA/V
=
CURRENT MODE
POWER STAGE
g
m
=
+
PL
) across the feedback divider may
780mV
SHDN
SW
FB
V
IN
Figure 11. A Good PCB Layout Ensures Proper, Low EMI Operation
R1
R2
: VIAS TO LOCAL GROUND PLANE
: OUTLINE OF LOCAL GROUND PLANE
C
ESR
C1
PL
+
3493 F10
OUT
C1
C2
D1
conditions, including load current, input voltage and tem-
perature. The LT1375 data sheet contains a more thorough
discussion of loop compensation and describes how to
test the stability using a transient load.
PCB Layout
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Figure 11 shows the
recommended component placement with trace, ground
plane and via locations. Note that large, switched currents
fl ow in the LT3493’s V
and the input capacitor (C2). The loop formed by these
components should be as small as possible and tied to
system ground in only one place. These components, along
with the inductor and output capacitor, should be placed on
the same side of the circuit board, and their connections
should be made on that layer. Place a local, unbroken ground
plane below these components, and tie this ground plane
to system ground at one location, ideally at the ground
terminal of the output capacitor C1. The SW and BOOST
nodes should be as small as possible. Finally, keep the
FB node small so that the ground pin and ground traces
will shield it from the SW and BOOST nodes. Include vias
near the exposed GND pad of the LT3493 to help remove
heat from the LT3493 to the ground plane.
C1
3493 F11
IN
SYSTEM
GROUND
V
and SW pins, the catch diode (D1)
OUT
3493fb

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