LT5554IUH-PBF LINER [Linear Technology], LT5554IUH-PBF Datasheet - Page 26
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LT5554IUH-PBF
Manufacturer Part Number
LT5554IUH-PBF
Description
Broadband Ultra Low Distortion 7-Bit Digitally Controlled VGA
Manufacturer
LINER [Linear Technology]
Datasheet
1.LT5554IUH-PBF.pdf
(32 pages)
LT5554
APPLICATIONS INFORMATION
Evaluation Board
Figure 21 shows the schematic of the LT5554 evaluation
board. Transformer T2 is TC2-1T and resistor R5 + R6 =
134Ω (R
layout are shown in Figures 22 through Figure 27. The
board control J5 edge connector (40PINS SMT-TB) allows
easy access to LT5554 component pins. Alternatively or
combined with J5, 14 test points (turrets) for signals and
two for GND are also available. The board is powered with
a single supply in 4.75V to 5.25V at V
J5 connector or turrets). Connecting the ENABLE pin to
26
OUT
= 50Ω G
J6
P
(J3) = 13.2dB). The silkscreen and
V
DEC
100Ω
R16
1μF
0Ω
R8
C5
Figure 20. Timing Test for PG6 and STROBE (Simplifi ed Schematic)
47nF
C16
PG5
CC
R25
10k
PG1
PG2
1
2
3
4
5
6
7
8
and V
R21
R28
R32
10k
0Ω
0Ω
GND
GND
DEC
IN
IN
DEC
GND
GND
32
+
–
9
PG1
PG5
PG6
47nF
C27
31
10
CCO
GND
GND
100Ω
R22
R29
R33
R26
10k
10k
0Ω
30
11
(either
PG2
PG6
29
12
PG3
PG0
LT5554
R23
10k
R30
0Ω
R27
0Ω
R20
10k
28
13
GND
GND
PG0
100Ω
V
and STROBE inputs will have TTL levels (DC-coupled)
when MODE = 5V (same power supply). To set LT5554 for
maximum gain (G
and STROBE can be connected to 5V supply. Alternatively,
a 2.2V power supply at V
set same G
J1 (input) and J3 (output) are the default board signal
ports for evaluation with 50Ω single ended test system. For
differential evaluation, the board J11 and J33 connectors
must be reconfi gured.
R24
R31
R34
10k
0Ω
CC
STROBE
STROBE
27
14
PG4
supply enables the LT5554 part. PGx gain control
47nF
47nF
C17
C28
26
15
PG4
PG3
GND
GND
47nF
C88
25
16
MAX
MODE
OUT
GND
OUT
GND
GND
GND
ENB
V
V
100Ω
CC
CC
R17
–
+
state.
5554 F20
24
23
22
21
20
19
18
17
V
MAX
PG
J7
) in transparent-mode, all seven PGx
C8
0.1μF
0.1μF
PG
C4
pin and STROBE turret will
V
ENABLE
CC
C6
47nF
MODE
5554f