CS8421_06 CIRRUS [Cirrus Logic], CS8421_06 Datasheet - Page 15
CS8421_06
Manufacturer Part Number
CS8421_06
Description
32-bit, 192 kHz Asynchronous Sample Rate Converter
Manufacturer
CIRRUS [Cirrus Logic]
Datasheet
1.CS8421_06.pdf
(38 pages)
- Current page: 15 of 38
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DS641F1
3. TYPICAL CONNECTION DIAGRAMS
* When no external master clock is supplied to the part, both input and output must be set to Slave Mode for the
part to operate properly. This is done by connecting the MS_SEL pin to ground through a resistance of 0 Ω to 1 k Ω
+ 1% as stated in
on page
** The connection (VL or GND) and value of these two resistors determines the mode of operation for the input
and output serial ports as described in
1 kΩ
19.
*
Table 1, “Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL),”
Hardware Control
Settings
Figure 5. Typical Connection Diagram, No External Master Clock
Source
**
0.1 µF
Serial
Audio
Table 2 on page 19
ILRCK
ISCLK
SDIN
TDM_IN
MS_SEL
SAIF
SAOF
SRC_UNLOCK
BYPASS
RST
+2.5 V
VD
GND
CS8421
and
Table 3 on page
GND
VL
SDOUT
+3.3 V or +5.0 V
OLRCK
OSCLK
XTI
19.
0.1 µF
Device
Serial
Audio
Input
CS8421
15
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