CS8422 CIRRUS [Cirrus Logic], CS8422 Datasheet - Page 67

• Manufacturer Part Number: CS8422
• Description: 24-bit, 192 kHz, Asynchronous Sample Rate Converter with
• Manufacturer: CIRRUS [Cirrus Logic]

DS692PP1
12.4.2 Accessing the E buffer
There are a number of conditions that will inhibit the buffer update. If the CS_UPDATE bit in
tus (16h)”
bit in
update.
The user can monitor the incoming data by reading the E buffer, which is mapped into the register space of
the CS8422, through the control port.
The user can configure the interrupt enable register to cause interrupts to occur whenever D to E buffer
transfers occur. This allows determination of the allowable time periods to interact with the E buffer.
Also provided is a D to E inhibit bit in the
“long” control port interactions are occurring or for debugging purposes.
A flowchart for reading the E buffer is shown in
there is a substantial time interval until the next D to E transfer (approximately 192 frames worth of time).
This is usually enough time to access the E data without having to inhibit the next transfer.
“Receiver Status (16h)”
is set to ‘0’, the only condition that will inhibit the update is PLL phase unlock. If the CS_UPDATE
From
AES3
Receiver
C Data Serial Output
Figure 33. Channel Status Data Buffer Structure
Figure 34. Flowchart for Reading the E Buffer
Received
Data
Buffer
D to E interrupt occurs
D
Return
24 words
is set to ‘1’, a biphase, confidence, parity, or CRC error will also inhibit the
“Receiver Data Control (04h)”
Optionally set D to E inhibit
If set, clear D to E inhibit
Figure
E
8-bits
Read E data
A
34. Since a D to E interrupt occurs just after reading,
5 words
8-bits
B
register. This may be used whenever
Registers
Control
Port
“Receiver Sta-
CS8422
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