LMC7101QM5 NSC [National Semiconductor], LMC7101QM5 Datasheet - Page 19

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LMC7101QM5

Manufacturer Part Number
LMC7101QM5
Description
Tiny Low Power Operational Amplifier with Rail-to-Rail Input and Output
Manufacturer
NSC [National Semiconductor]
Datasheet

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4.0 CAPACITIVE LOAD TOLERANCE
The LMC7101 can typically directly drive a 100 pF load with
V
lower is the most sensitive configuration. Direct capacitive
loading reduces the phase margin of op amps. The combina-
tion of the op amp's output impedance and the capacitive load
induces phase lag. This results in either an underdamped
pulse response or oscillation.
Capacitive load compensation can be accomplished using
resistive isolation as shown in Figure 4. This simple technique
is useful for isolating the capacitive input of multiplexers and
A/D converters.
5.0 COMPENSATING FOR INPUT CAPACITANCE WHEN
USING LARGE VALUE FEEDBACK RESISTORS
When using very large value feedback resistors, (usually
> 500 kΩ) the large feed back resistance can react with the
input capacitance due to transducers, photodiodes, and cir-
cuit board parasitics to reduce phase margins.
The effect of input capacitance can be compensated for by
adding a feedback capacitor. The feedback capacitor (as in
Figure 5), C
S
= 15V at unity gain without oscillating. The unity gain fol-
f
is first estimated by:
FIGURE 4. Resistive Isolation
of a 330 pF Capacitive Load
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19
which typically provides significant overcompensation.
Printed circuit board stray capacitance may be larger or small-
er than that of a breadboard, so the actual optimum value for
C
the actual circuit. (Refer to the LMC660 quad CMOS amplifier
data sheet for a more detailed discussion.)
F
FIGURE 5. Cancelling the Effect of Input Capacitance
may be different. The values of C
R
1
C
IN
or
R
2
C
F
f
should be checked on
www.national.com
1199112

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