MAX8513 MAXIM [Maxim Integrated Products], MAX8513 Datasheet - Page 12

• Manufacturer Part Number: MAX8513
• Description: Wide-Input, High-Frequency, Triple-Output Supplies with Voltage Monitor and Power-On Reset
• Manufacturer: MAXIM [Maxim Integrated Products]

Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
12
COMP1
NAME
PGND
FREQ
DRV2
SUP2
GND
PFO
BST
PVL
FB1
REF
FB2
PIN
PFI
DH
DL
LX
VL
______________________________________________________________________________________
MAX8513
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
MAX8514
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
Power-Fail Input. Connect PFI to an external resistive-divider between IN, PFI, and GND.
PFI senses V
20mV of hysteresis.
Power-Fail Output. Open-drain output that goes low if V
OUT1 High-Side Gate-Drive Output. DH drives the high-side N-channel MOSFET (Q1 in the
Typical Applications Circuits). DH is a floating driver output that swings from LX to BST.
OUT1 High-Side Driver Return Path. The high-side FET driver uses BST and LX for its
respective high and low-side supplies.
OUT1 Boost Capacitor Connection for High-Side Gate Drive. Connect a 0.1µF ceramic
capacitor from BST to LX with a less than 5mm trace length.
OUT1 Low-Side Gate-Drive Output. DL drives the low-side N-channel MOSFET (Q2 in the
Typical Applications Circuits). DL swings from 0 to V
OUT1 Gate-Drive Supply Bypass Connection. Connect PVL to VL through a 10 resistor
(R15), and bypass PVL to PGND with a minimum 1µF capacitor (C1).
Power-Ground Connection and Low-Side Supply for Dl Driver
Internal +5V Linear-Regulator Bypass Pin. Bypass VL to GND with a minimum 2.2µF
ceramic capacitor (C10) and 5mm or less of trace length. VL should be connected to IN
when V
OUT1 Compensation Node. See the OUT1 Compensation section.
OUT1 Feedback Input. Connect a resistive-divider (R1, R2) from OUT1 to FB1 to GND to
regulate FB1 at 1.25V.
Oscillator Frequency-Set Input. A resistor from FREQ to GND sets the oscillator frequency
from 300kHz to 1.4MHz (f = 15MHz x k / R
is used at SYNC/EN, and the SYNC/EN input frequency should be within ±30% of the
frequency set by R
1.25V Refer ence O utp ut. C onnect a 0.1µF or l ar g er cer am i c cap aci tor ( C 9) fr om RE F to GN D .
Analog/Signal Ground
OUT2 Feedback Input. Connect a resistive-divider (R5, R6) from OUT2 to FB2 to GND to
regulate FB2 to 0.8V.
OUT2 Gate Drive. DRV2 connects to the gate of an external N-channel MOSFET to form a
positive linear voltage regulator.
Supply Input for DRV2. Connect to a voltage source of at least 1V above the maximum
desired DRV2 gate voltage.
IN
< 5.5V.
IN
to detect voltage failure. Trip falling threshold at this input is 1.22V, with
FREQ
.
FUNCTION
FREQ
). R
PVL
FREQ
PFI
.
is still required if an external clock
< 1.22V.
Pin Description