MAX8550-MAX8551 MAXIM [Maxim Integrated Products], MAX8550-MAX8551 Datasheet - Page 26

• Manufacturer Part Number: MAX8550-MAX8551
• Description: Integrated DDR Power-Supply Solutions for Desktops, Notebooks, and Graphic Cards
• Manufacturer: MAXIM [Maxim Integrated Products]

Integrated DDR Power-Supply Solutions for
Desktops, Notebooks, and Graphic Cards
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention. If
possible, mount all of the power components on the top
side of the board, with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
• Keep the high-current paths short, especially at the
• Keep the power traces and load connections short.
• The LX and PGND1 connections to the low-side
• When trade-offs in trace lengths must be made, it is
Figure 9. Voltage-Positioned Output
26
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance caus-
es a measurable efficiency penalty.
MOSFET for current sensing must be made using
Kelvin-sense connections.
preferable to allow the inductor-charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
______________________________________________________________________________________
PC Board Layout Guidelines
AV
FB
DD
MAX8550/
MAX8551
PGND1
GND
OUT
V
BST
DH
DL
DD
LX
IN
• Route high-speed switching nodes (BST, LX, DH,
• Input ceramic capacitors must be placed as close
The capacitor (or capacitors) at VTT should be placed
as close to VTT and PGND2 (pins 12 and 11) as possi-
ble to minimize the series resistance/inductance of the
trace. The PGND2 side of the capacitor must be short
with a low-impedance path to the exposed pad under-
neath the IC. The exposed pad must be star-connected
to GND (pin 24), PGND1 (pin 23), and PGND2 (pin 11).
A narrower trace can be used to connect the output
voltage on the VTT side of the capacitor back to VTTS
(pin 9). However, keep this trace well away from poten-
tially noisy signals such as PGND1 or PGND2. This
prevents noise from being injected into the error ampli-
fier’s input. For best performance, the VTTI bypass
capacitor must be placed as close to VTTI (pin 13) as
possible. REFIN (pin 14) should be separately routed
with a clean trace and adequately bypassed to GND.
Refer to the MAX8550 evaluation kit data sheet for PC
board guidelines.
side MOSFET or between the inductor and the out-
put filter capacitor.
and DL) away from sensitive analog areas (REF, FB,
and ILIM).
as possible to the high-side MOSFET drain and the
low-side MOSFET source. Position the MOSFETs so
the impedance between the input capacitor termi-
nals and the MOSFETs is as low as possible.
Special Layout Considerations for LDO Section
+5V BIAS
SUPPLY
V
IN
R
POS
POSITIONED
VOLTAGE-
OUTPUT