74AUP2G08 PHILIPS [NXP Semiconductors], 74AUP2G08 Datasheet

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74AUP2G08

Manufacturer Part Number
74AUP2G08
Description
Low-power dual 2-input AND gate
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet

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1. General description
2. Features and benefits
The 74AUP2G08 provides the dual 2-input AND function.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
CC
74AUP2G08
Low-power dual 2-input AND gate
Rev. 5 — 1 December 2011
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
range from 0.8 V to 3.6 V.
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1 000 V
circuitry provides partial power-down mode operation
CC
range from 0.8 V to 3.6 V.
CC
= 0.9 A (maximum)
CC
Product data sheet
OFF
. The I
OFF

Related parts for 74AUP2G08

74AUP2G08 Summary of contents

Page 1

... Low-power dual 2-input AND gate Rev. 5 — 1 December 2011 1. General description The 74AUP2G08 provides the dual 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V This device ensures a very low static and dynamic power consumption across the entire V range from 0 ...

Page 2

... Marking Table 2. Marking codes Type number 74AUP2G08DC 74AUP2G08GT 74AUP2G08GF 74AUP2G08GD 74AUP2G08GM 74AUP2G08GN 74AUP2G08GS [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 001aah788 Fig 1 ...

Page 3

... Fig 7. Pin configuration SOT902-1 SOT902 All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate 74AUP2G08 GND 001aae237 ...

Page 4

... Conditions Active mode Power-down mode 0 3 All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate Output Min Max 0.5 +4.6 50 -  ...

Page 5

... 3 3 GND GND All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate Min Typ Max 0.70  0.65  1 2 0.30  0.35  ...

Page 6

... GND 0 3  All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate Min Typ Max 0.70  0.65  1 2 0.30  0.35  ...

Page 7

... 0 3  GND. CC All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate Min Typ Max 0.75  0.70  1 2 0.25  0.30  ...

Page 8

... All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate C = 40 C to +125 C Unit T T amb amb [1] Min Typ Max ...

Page 9

... Input V M 0.5  All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate Figure C = 40 C to +125 C Unit T T amb ...

Page 10

... DUT R T 10. [ k M k. L All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate V EXT 5 kΩ 001aac521 of the pulse generator EXT ...

Page 11

... 0.27 0.23 2.1 2.4 0.5 0.17 0.08 1.9 2.2 REFERENCES JEDEC JEITA MO-187 All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate detail 3.2 0.40 0.21 0.4 0.2 0.13 3.0 ...

Page 12

... 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA - - - MO-252 All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate 4× ( EUROPEAN PROJECTION © NXP B.V. 2011. All rights reserved. SOT833-1 ISSUE DATE 07-11-14 07-12- ...

Page 13

... References JEDEC JEITA MO-252 All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate detail X (2) (8× European projection © NXP B.V. 2011. All rights reserved. SOT1089 sot1089_po Issue date 10-04-09 10-04- ...

Page 14

... 3.1 0.5 0.15 0.6 0.5 1.5 2.9 0.3 0.4 0.05 REFERENCES JEDEC JEITA - - - All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate detail 0.1 0.05 0.05 0.1 EUROPEAN PROJECTION SOT996-2 ISSUE DATE 07-12-18 07-12-21 © ...

Page 15

... 1.65 0.35 0.15 0.55 0.5 0.1 1.55 0.25 0.05 REFERENCES JEDEC JEITA MO-255 - - - All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate detail 0.05 0.05 0.05 EUROPEAN PROJECTION SOT902 ISSUE DATE ...

Page 16

... 1.05 0.35 0.40 1.00 0.55 0.3 0.30 0.35 0.95 0.27 0.32 References JEDEC JEITA All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate (2) (4× European projection SOT1116 sot1116_po Issue date 10-04-02 10-04-07 © NXP B.V. 2011. All rights reserved ...

Page 17

... 1.05 0.35 0.40 1.00 0.55 0.35 0.30 0.35 0.95 0.27 0.32 References JEDEC JEITA All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate (2) (4× European projection SOT1203 sot1203_po Issue date 10-04-02 10-04-06 © NXP B.V. 2011. All rights reserved ...

Page 18

... Product data sheet Product data sheet Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate Change notice Supersedes - 74AUP2G08 v.4 - 74AUP2G08 v.3 - 74AUP2G08 v.2 - 74AUP2G08 v © NXP B.V. 2011. All rights reserved ...

Page 19

... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate © NXP B.V. 2011. All rights reserved ...

Page 20

... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 5 — 1 December 2011 74AUP2G08 Low-power dual 2-input AND gate © NXP B.V. 2011. All rights reserved ...

Page 21

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 1 December 2011 Document identifier: 74AUP2G08 ...

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