MAX8710 MAXIM [Maxim Integrated Products], MAX8710 Datasheet - Page 21

• Manufacturer Part Number: MAX8710
• Description: Low-Cost, Linear-Regulator LCD Panel Power Supplies
• Manufacturer: MAXIM [Maxim Integrated Products]

Adjust the linear-regulator output voltage by connecting
a resistive voltage-divider from the linear-regulator out-
put AV
(Figure 1). Select the lower resistor of divider R2 in the
10kΩ to 50kΩ range. Calculate upper resistor R1 with
the following equation:
where V
linear regulator.
The linear regulator’s output stage consists of a pnp pass
transistor. Rapid movements of the input voltage must be
avoided since the movement can be coupled into the
base of the transistor through the base-to-emitter junction
capacitance. The input capacitor reduces the current
peaks drawn from the input supply and slows down the
input voltage movement. One 10µF ceramic capacitor is
used in the Typical Operating Circuits (Figures 1, 2, and
3) because of the high source impedance seen in typical
lab setups. Actual applications usually have much lower
source impedance, since the linear regulator typically
runs directly from the output of another regulated supply
and can operate with less input capacitance.
The output capacitor and its equivalent series resistance
(ESR) affect the linear regulator’s stability and transient
response. The MAX8710/MAX8711/MAX8712 can deliver
at least 300mA continuously and are stable with a 4.7µF
output capacitor. The MAX8761 can deliver at least
500mA of output current and is stable with a 10µF output
capacitor.
The typical load on the linear regulator for source-driver
applications is a large pulsed load, with a peak current
of approximately 1A and pulse width of approximately
2µs. The shape of the pulse is close to a triangle, so it
is equivalent to a square pulse with 1A height and 1µs
pulse width. The total voltage dip during the pulsed
load transient also has two components: the ohmic dip
due to the output capacitor’s ESR, and the capacitive
dip caused by discharging the output capacitance:
DD
FBL
to GND with the center tap connected to FBL
= 2.5V (typ) is the regulation point of the
R
1
______________________________________________________________________________________
=
R
2
×
Output-Capacitor Selection
Design Procedure
⎛
⎜
⎝
Input-Capacitor Selection
Output-Voltage Selection
V
V
AVDD
FBL
Linear Regulator
−
1
⎞
⎟
⎠
Low-Cost, Linear-Regulator
LCD Panel Power Supplies
where I
is the pulse width. Higher capacitance and lower ESR
result in less voltage dip. The ESR dip can be ignored
when using ceramic output capacitors. Calculate the
minimum required capacitance for the maximum allowed
dip using:
The above equations are “worst case” and assume that
the linear regulator does not react to correct the output
voltage during the load pulse. In fact, the regulator is
fast enough to partially correct the output voltage, so
the actual dip may be smaller, or a smaller capacitor
may be acceptable. For the typical load pulse
described above, assuming the voltage dip must be
limited to 150mV, the minimum output capacitor is:
Because the regulator is able to limit the dip some-
what, the circuit of Figure 1 uses a 4.7µF/10µF
(MAX8710/MAX8761) output capacitor. The voltage
rating and temperature characteristics of the output
capacitor must also be considered.
The output capacitance and equivalent load resistance
determine the dominant pole. An internal parasitic
capacitance of the regulator creates a second pole.
This pole typically occurs at 100kHz, but can vary
between 60kHz and 140kHz depending on the process
variation. Since the pole occurs after the loop gain
crossover, it does not affect the loop stability. However,
canceling this pole with an additional zero can improve
the load-transient response. An additional zero
improves the closed-loop phase margin, thereby
improving the transient response. The feed-forward net-
work should be designed to get maximum positive
phase at unity gain frequency (f
A zero can be added by connecting a feed-forward
capacitor (C1) between OUTL and FBL as shown in
Figure 1. The frequency of the zero can be calculated
with the following equation:
PULSE
C
C
OUT MIN
OUT MIN
V
V
V
is the height of the pulse load, and t
DIP
DIP ESR
DIP C
(
(
(
( )
=
)
)
)
≈
V
≈
DIP ESR
≈
=
Feed-Forward Compensation
I
PULSE
1
I
I
(
PULSE
PULSE
A
0 15
.
×
V
)
C
DIP MAX
1
u
V
OUT
+
×
µ
).
×
×
(
s
V
t
PULSE
R
DIP C
t
=
PULSE
ESR
)
( )
6 7
.
µ
F
PULSE
21