V62C1161024L-100T MOSEL [Mosel Vitelic, Corp], V62C1161024L-100T Datasheet - Page 7

• Manufacturer Part Number: V62C1161024L-100T
• Description: Ultra Low Power 64K x 16 CMOS SRAM
• Manufacturer: MOSEL [Mosel Vitelic, Corp]

REV. 1.1 April 2001 V62C1161024L(L)
Notes (Write Cycle)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. When CE is low: I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should
11. For test conditions, see AC Test Condition, Figure A & B.
All write timing is referenced from the last valid address to the first transition address.
A write occurs during the overlap of a low CE and WE. A write begins at the latest transition among CE and WE going
low: A write ends at the earliest transition among CE going high and WE going high.
of write to the end of write.
t
t
t
If OE, CE and WE are in the Read Mode during this period, the I/O pins are in the output Low-Z state.
Inputs of opposite phase of the output must not be applied because bus contention can occur.
For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
If CE goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.
D
not be applied.
CW
AS
WR
OUT
is measured from the address valid to the beginning of write.
is measured from the later of CE going low to end of write.
is measured from the end of write to the address change.
is the read data of the new address.
7
t
WP
is measured from the beginning
V62C1161024L(L)