FXL2SD106BQX_11 FAIRCHILD [Fairchild Semiconductor], FXL2SD106BQX_11 Datasheet - Page 9

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FXL2SD106BQX_11

Manufacturer Part Number
FXL2SD106BQX_11
Description
Low-Voltage Dual-Supply 6-Bit Voltage Translator with Auto-Direction Sensing
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
© 2008 Fairchild Semiconductor Corporation
FXL2SD106 • Rev. 1.8.1
Input t
Input t
Input t
Input t
I
OHD
DATA
CONTROL
Figure 4. 3-STATE Output High Enable Time for
Figure 5. Active Output Rise Time and Dynamic
OUTPUT
R
R
V
R
R
≈ (C
IN
OUT
DATA
DATA
= t
= t
= t
= t
OUT
DATA
Figure 2. Waveform for Inverting and
OUT
L +
F
F
F
F
Max. data rate, f = 1/t
IN
= 2.0ns, 10% to 90%
= 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only
= 2.0ns, 10% to 90%
= 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only
C
V
I/O
Figure 7. Maximum Data Rate
OL
Non-inverting Functions
) x
t
PZH
Output Current High
Low Voltage Logic
ΔV
V
Δt
t
OUT
pxx
CCI
V
mi
/2
V
= (C
20% x V
x
t
t
W
rise
Time
L +
W
C
80% x V
I/O
CCO
) x
t
pxx
(20% – 80%) x V
V
V
CCI
CCO
mi
V
V
mo
/2
OH
t
RISE
V
GND
V
V
GND
V
CCI
CCO
CCA
OH
V
GND
CCI
CCO
9
Input t
Input t
Note:
15. V
Figure 3. 3-STATE Output Low Enable Time for Low
I
OLD
OUTPUT
OUTPUT
Figure 6. Active Output Fall Time and Dynamic
CONTROL
≈ (C
R
R
V
DATA
DATA
CCI
OUTPUT
Symbol
OUT
Vmi
= t
= t
t
Vmo
skew
VX
VY
L +
DATA
= V
F
F
OUT
(15)
= 2.0ns, 10% to 90%
= 2.5ns, 10% to 90%, @ Vi = 3.0V to 3.6V only
C
80% x V
I/O
= (t
CCA
Figure 8. Output Skew Time
t
) x
skew
pHLmax
V
OH
t
for control pin OE or Vmi = (V
PZL
Output Current Low
20% x V
ΔV
CCO
Δt
Voltage Logic
OUT
V
mo
– t
V
0.9 x V
0.1 x V
mi
pHLmin
V
= (C
V
CCO
V
t
CCO
fall
CCI
V
Vcc
Time
Y
mo
L +
/ 2
CCO
CCO
/ 2
)
C
or
I/O
(t
) x
pLHmax
(80% – 20%) x V
V
mo
– t
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t
V
t
skew
V
pLHmin
FALL
OL
mo
CCA
V
GND
V
CCA
OL
V
GND
V
GND
)
CCO
CCO
/ 2).
CCO

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