SSTL16857DGG PHILIPS [NXP Semiconductors], SSTL16857DGG Datasheet - Page 2

• Manufacturer Part Number: SSTL16857DGG
• Description: 14-bit SSTL_2 registered driver with differential clock inputs
• Manufacturer: PHILIPS [NXP Semiconductors]

1. C
Philips Semiconductors
FEATURES
DESCRIPTION
The SSTL16857 is a 14-bit SSTL_2 registered driver with differential
clock inputs. Both V
however. V
V
be used for standard stub-series applications or capacitive loads.
Master reset (RESET) asynchronously resets all registers to zero.
The SSTL16857 is intended to be incorporated into standard DIMM
(Dual In-Line Memory Module) designs defined by JEDEC, such as
DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules.
Different from traditional SDRAM, DDR SDRAM transfers data on
both clock edges (rising and falling), thus doubling the peak bus
bandwidth. A DDR DRAM rated at 100 MHz will have a burst rate of
200 MHz. The modules require between 23 and 27 registered
control and address lines, so two 14-bit wide devices will be used on
each module. The SSTL16857 is intended to be used for SSTL_2
input and output signals.
The device data inputs consist of differential receivers. One
differential input is tied to the input pin while the other is tied to a
reference input pad, which is shared by all inputs.
The clock input is fully differential to be compatible with DRAM
devices that are installed on the DIMM. However, since the control
inputs to the SDRAM change at only half the data rate, the device
must only change state on the positive transition of the CLK signal.
In order to be able to provide defined outputs from the device even
before a stable clock has been supplied, the device must support an
asynchronous input pin (reset), which when held to the LOW state
will assume that all registers are reset to the LOW state and all
outputs drive a LOW signal as well.
QUICK REFERENCE DATA
GND = 0 V; T
NOTES:
ORDERING INFORMATION
48-Pin Plastic TSSOP Type I
1999 Sep 30
REF
Stub-series terminated logic for 2.5V VDDQ (SSTL_2)
Optimized for DDR (Double Data Rate) SDRAM applications
Supports SSTL_2 signal inputs and outputs
Flow-through architecture optimizes PCB layout
Meets SSTL_2 class I and class II specifications
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000 V per MIL STD 833 Method 3015
and 200 V per Machine Model
Full DDR solution provided when used with PCK857 and CBT3857
14-bit SSTL_2 registered driver with
differential clock inputs
f
i
PD
= input frequency in MHz; C
(C
normally at 0.5*V
SYMBOL
t
L
is used to determine the dynamic power dissipation (P
PHL
DDQ
C
/t
V
I
amb
PLH
CC
must not exceed V
PACKAGES
2
= 25 C; t
CC
f
o
DDQ
) = sum of the outputs.
and V
Propagation delay; CLK to Qn
Input capacitance
r
. The outputs support class I which can
=t
DDQ
f
v2.5 ns
L
support 2.5V and 3.3V operation
CC
= output load capacity in pF; f
. Inputs are SSTL_2 type with
PARAMETER
TEMPERATURE RANGE
0 C to +70 C
D
in W) P
o
= output frequency in MHz; V
C
V
L
CC
2
= 30 pF; V
D
= 2.5V
= C
PIN CONFIGURATION
CONDITIONS
PD
DDQ
V
CC
= 2.5 V
2
x f
SSTL16857 DGG
ORDER CODE
i
VDDQ
VDDQ
) (C
VDDQ
VDDQ
VDDQ
GND
GND
GND
GND
GND
CC
Q10
Q12
Q13
Q14
Q11
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
= supply voltage in V;
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
L
1
2
3
4
5
6
7
8
9
V
CC
2
TYPICAL
1.8
2.9
f
SW00311
o
) where:
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SSTL16857
D1
D2
GND
VCC
D3
D4
D5
D6
D7
CLK–
CLK+
VCC
GND
VREF
RESET
D8
D9
D10
D11
D12
VCC
GND
D13
D14
Product specification
DWG NUMBER
853-2155 22448
SOT362-1
UNIT
pF
ns