24AA32A-P MICROCHIP [Microchip Technology], 24AA32A-P Datasheet

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24AA32A-P

Manufacturer Part Number
24AA32A-P
Description
32K 1.8V I 2 C O Serial EEPROM
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
FEATURES
• Single supply with operation down to 1.8V
• 2-wire serial interface bus, I
• 100 kHz (1.8V) and 400 kHz (5V) compatibility
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Hardware write protect
• 1,000,000 Erase/Write cycles guaranteed
• 32 byte page or byte write modes available
• Schmitt trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24AA32A is a 4K x 8
(32K bit) Serial Electrically Erasable PROM capable of
operation across a broad voltage range (1.8V to 6.0V).
It has been developed for advanced, low power applica-
tions such as personal communications or data acqui-
sition. The 24AA32A also has a page-write capability of
up to 32 bytes of data. The 24AA32A is capable of both
random and sequential reads up to the 32K boundary.
Functional address lines allow up to eight 24AA32A
devices on the same bus, for up to 256K bits address
space. Advanced CMOS technology and broad voltage
range make this device ideal for low-power/low-voltage,
nonvolatile code and data applications. The 24AA32A
is available in the standard 8-pin plastic DIP and both
150 mil and 200 mil SOIC packages.
I
2
C is a trademark of Philips Corporation.
1996 Microchip Technology Inc.
- Maximum write current 3 mA at 6.0V
- Standby current 1 A max at 1.8V
same bus for up to 256K bits total memory
- Commercial (C):
0 C to +70 C
32K 1.8V I
2
C
This document was created with FrameMaker 4 0 4
compatible
2
C Serial EEPROM
Preliminary
PACKAGE TYPE
BLOCK DIAGRAM
SDA
I/O
V
V
CONTROL
PDIP
SOIC
CC
SS
LOGIC
I/O
SCL
Vss
A0..A2
Vss
A0
A1
A2
A0
A1
A2
24AA32A
WP
CONTROL
MEMORY
LOGIC
1
2
3
4
WP
1
2
3
4
XDEC
8
7
6
5
8
7
6
5
DS21162B-page 1
HV GENERATOR
PAGE LATCHES
R/W CONTROL
SENSE AMP
Vcc
WP
SCL
SDA
EEPROM
ARRAY
YDEC
Vcc
WP
SCL
SDA

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24AA32A-P Summary of contents

Page 1

... It has been developed for advanced, low power applica- tions such as personal communications or data acqui- sition. The 24AA32A also has a page-write capability bytes of data. The 24AA32A is capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to eight 24AA32A devices on the same bus, for up to 256K bits address space ...

Page 2

... ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* V ...................................................................................7.0V CC All inputs and outputs w.r.t. V ............... -0. Storage temperature ..................................... -65˚C to +150˚C Ambient temp. with power applied ................ -65˚C to +125˚C Soldering temperature of leads (10 seconds) ............. +300˚C ESD protection on all pins *Notice: Stresses above those listed under “Maximum Ratings” ...

Page 3

... Schmitt trigger inputs which provide improved noise T HIGH DAT SU DAT STA T AA Preliminary 24AA32A Units Remarks kHz (Note 1) ns (Note 1) ns After this period the first clock pulse is generated ns Only relevant for repeated START condition ns ns ...

Page 4

... NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24AA32A) will leave the data line HIGH to enable the master to generate the STOP condition. (D) ...

Page 5

... SDA bus checking the device type identifier being transmitted. Upon receiving a 1010 code and appropri- ate device select bits, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24AA32A will select a read or write operation. Control Operation ...

Page 6

... The next byte is the least sig- nificant address byte. After receiving another acknowl- edge signal from the 24AA32A the master device will transmit the data word to be written into the addressed memory location ...

Page 7

... To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24AA32A as part of a write operation (R/W bit set to zero). After the word address is sent, the master gener- ates a start condition following the acknowledge. This terminates the write operation, but not before the inter- nal address pointer is set ...

Page 8

... The device select bits A2, A1, A0 can be used to expand the contiguous address space for up to 256K bits by adding up to eight 24AA32A's on the same bus. In this case, software can use A0 of the control byte as address bit A12 address bit A13, and A2 as address bit A14 ...

Page 9

... PIN DESCRIPTIONS 7.1 A0, A1, A2 Chip Address Inputs The A0..A2 inputs are used by the 24AA32A for multi- ple device operation and conform to the 2-wire bus standard. The levels applied to these pins define the address block occupied by the device in the address map. A particular device is selected by transmitting the corresponding bits (A2, A1, A0) in the control byte (Figure 3-3) ...

Page 10

... NOTES: DS21162B-page 10 Preliminary 1996 Microchip Technology Inc. ...

Page 11

... Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 24AA32A – /P Package: Temperature Range: Device: 1996 Microchip Technology Inc Plastic DIP (300 mil Body), 8-lead ...

Page 12

W ORLDWIDE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 ...

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