93LC76-SN MICROCHIP [Microchip Technology], 93LC76-SN Datasheet - Page 9

• Manufacturer Part Number: 93LC76-SN
• Description: 8K/16K 2.5V Microwire Serial EEPROM
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 3-8:
4.0
4.1
A HIGH level selects the device. A LOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated will be
completed, regardless of the CS input signal. If CS is
brought LOW during a program cycle, the device will go
into standby mode as soon as the programming cycle
is completed.
CS must be LOW for 250 ns minimum (T
consecutive instructions. If CS is LOW, the internal con-
trol logic is held in a RESET status.
4.2
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93LC76/86.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be continued
anytime with respect to clock HIGH time (T
clock LOW time (T
ter freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
1996 Microchip Technology Inc.
CLK
DO
CS
DI
ORG=VCC, 8 X’s
ORG=VSS, 9 X’s
PIN DESCRIPTIONS
Chip Select (CS)
Serial Clock (CLK)
ERAL
CKL
1
). This gives the controlling mas-
Guaranteed at VCC = +4.5V to +6.0V.
0
HIGH IMPEDANCE
0
CSL
1
) between
CKH
) and
0
Preliminary
X
After detection of a start condition the specified number
of clock cycles (respectively LOW to HIGH transitions of
CLK) must be provided. These clock cycles are
required to clock in all opcode, address, and data bits
before an instruction is executed (see Table 1-4 through
Table 1-7 for more details). CLK and DI then become
don't care inputs waiting for a new start condition to be
detected.
4.3
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
4.4
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (T
edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available when CS is high. It will be
displayed until the next start bit occurs as long as CS
stays high.
4.5
When ORG is connected to V
nization is selected. When ORG is tied to V
memory organization is selected. There is an internal
pull-up resistor on the ORG pin that will select x16 orga-
nization when left unconnected.
4.6
This pin allows the user to enable or disable the ability
to write data to the memory array. If the PE pin is floated
or tied to V
pin is tied to V
is an internal pull-up on this device that enables pro-
gramming if this pin is left floating.
...
Note:
X
Data In (DI)
Data Out (DO)
Organization (ORG)
Program Enable (PE)
CC
CS must go LOW between consecutive
instructions, except when performing a
sequential read (Refer to Section 3.1 for
more detail on sequential reads).
, the device can be programmed. If the PE
SS
, programming will be inhibited. There
T
EC
BUSY
93LC76/86
CC
, the x16 memory orga-
PD
READY
T
CZ
after the positive
DS21131C-page 9
STANDBY
SS
, the x8