AT24C256C-CUL-T ATMEL [ATMEL Corporation], AT24C256C-CUL-T Datasheet - Page 7

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AT24C256C-CUL-T

Manufacturer Part Number
AT24C256C-CUL-T
Description
serial electrically erasable and programmable read-only memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
8568C–SEEPR–5/10
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol
reset by following these steps:
a)
b)
c)
The device is ready for next communication after above steps has been completed.
Figure 4-3.
SDA
Figure 4-4.
SDA OUT
SCL
SDA IN
Create a start bit condition,
Clock nine cycles,
Create another start bit followed by stop bit condition as shown below.
SCL
Start bit
Software Reset
Bus Timing
t
SU.STA
1
2
t
HD.STA
t
t
F
LOW
t
AA
Dummy Clock Cycles
3
t
HIGH
t
HD.DAT
t
LOW
8
t
t
SU.DAT
DH
9
Start bit
Atmel AT24C256C
t
R
Stop bit
t
SU.STO
t
BUF
7

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