AT24C512B-10PU-1.8 ATMEL [ATMEL Corporation], AT24C512B-10PU-1.8 Datasheet - Page 6
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AT24C512B-10PU-1.8
Manufacturer Part Number
AT24C512B-10PU-1.8
Description
Two-wire Serial EEPROM 512K (65,536 x 8) with Three Device Address Inputs
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT24C512B-10PU-1.8.pdf
(18 pages)
Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Note:
6
1. The write cycle time t
AT24C512B [Preliminary]
SDA
SCL
WORDn
8th BIT
WR
is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
STANDBY MODE: The AT24C512B features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
ACK
CONDITION
STOP
t wr
(1)
CONDITION
START
5112A–SEEPR–8/05