AT25128-10CC-1.8 ATMEL [ATMEL Corporation], AT25128-10CC-1.8 Datasheet
AT25128-10CC-1.8
Related parts for AT25128-10CC-1.8
AT25128-10CC-1.8 Summary of contents
Page 1
... The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT25128 is available in space saving 8-pin PDIP, JEDEC SOIC, and 14-pin and 20-pin TSSOP packages. ...
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... Description (Continued) The AT25128 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE. BLOCK WRITE protection is enabled by programming the status register with one of four blocks of write protection ...
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... MHz -100 AT25128 = +5.0V (unless otherwise noted). CC Max Units Conditions OUT +1.8V to +5.5V, CC Min Typ Max 1.8 3.6 2.7 5.5 4.5 5.5 3.0 5.0 0.1 0.2 0.5 0.5 2.0 -3.0 3.0 -3.0 3 ...
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... CS Hold Time CSH t Data In Setup Time SU t Data In Hold Time H t Hold Setup Time HD t Hold Hold Time CD t Output Valid V t Output Hold Time HO t Hold to Output Low Z LZ AT25128 4 = -40°C to +85° Voltage Min 4.5 - 5.5 0 2.7 - 5.5 0 1.8 - 3.6 0 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 200 2.7 - 5.5 300 1 ...
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... AC Characteristics (Continued) Symbol Parameter t Hold to Output High Output Disable Time DIS t Write Cycle Time WC Voltage Min 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 AT25128 Max Units 100 100 ns 100 250 250 ns 1000 ...
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... The WP pin function is blocked when the WPEN bit in the status register is ”0". This will allow the user to install the AT25128 in a system with the WP pin tied to ground and still be able to write to the status regis- ter. All WP pin functions are enabled when the WPEN bit is set to “ ...
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... Functional Description The AT25128 is designed to interface directly with the syn- chronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25128 utilizes an 8 bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are trans- ferred with the MSB first ...
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... STATUS REGISTER instruction is enabled during the Protected Protected WRITE programming cycle. Writable Writable The AT25128 is capable of a 32-byte PAGE WRITE op- Protected Protected eration. After each byte of data is received, the five low Writable Protected order address bits are internally incremented by one; the ...
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... Timing Diagrams (for SPI Mode 0 (0,0)) Synchronous Data Timing CSS V IH SCK HI WREN Timing WRDI Timing VALID AT25128 CSH t t DIS HO HI-Z 9 ...
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... RDSR Timing SCK INSTRUCTION SI HIGH IMPEDANCE SO WRSR Timing READ Timing AT25128 MSB DATA OUT ...
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... WRITE Timing HOLD Timing CS SCK HOLD AT25128 ...
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... AT25640T2-10TC 0.5 2100 AT25128-10PC-2.7 AT25128-10SC-2.7 AT25128N1-10SC-2.7 AT25128T2-10TC-2.7 0.2 500 AT25128-10PC-1.8 AT25128-10SC-1.8 AT25128N1-10SC-1.8 AT25128T2-10TC-1.8 2.0 2100 AT25128-10PI AT25128-10SI AT25128N1-10SI AT25128T2-10TI 0.5 2100 AT25128-10PI-2.7 AT25128-10SI-2.7 AT25128N1-10SI-2.7 AT25128T2-10TI-2.7 0.2 500 AT25128-10PI-1.8 AT25128-10SI-1.8 AT25128N1-10SI-1.8 AT25128T2-10TI-1.8 Package Type Options Package Operation Range 8P3 Commercial 14S ( 16S1 20T 8P3 Commercial ...