24C65-EP MICROCHIP [Microchip Technology], 24C65-EP Datasheet

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24C65-EP

Manufacturer Part Number
24C65-EP
Description
64K 5.0V I 2 C Smart Serial EEPROM
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
FEATURES
• Voltage operating range: 4.5V to 5.5V
• Industry standard two-wire bus protocol, I
• 8 byte page, or byte modes available
• 2 ms typical write cycle time, byte or page
• 64-byte input cache for fast write loads
• Up to eight devices may be connected to the
• Including 400 KHz compatibility
• Programmable block security options
• Programmable endurance options
• Schmitt trigger, filtered inputs for noise suppres-
• Output slope control to eliminate ground bounce
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Endurance:
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP/SOIC packages
• Temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24C65 is a “smart” 8K x
8 Serial Electrically Erasable PROM (EEPROM). This
device has been developed for advanced, low power
applications such as personal communications, and
provides the systems designer with flexibility through
the use of many new user-programmable features. The
24C65
ultra-high-endurance memory for data that changes
frequently. The remainder of the array, or 60K bits, is
rated at 1,000,000 ERASE/WRITE (E/W) cycles guar-
anteed. The 24C65 features an input cache for fast
write loads with a capacity of eight pages, or 64 bytes.
This device also features programmable security
I
Smart Serial is a trademark of Microchip Technology Inc.
2
C is a trademark of Philips Corporation.
1996 Microchip Technology Inc.
- Peak write current 3 mA at 5.5V
- Maximum read current 150 A at 5.5V
- Standby current 1 A typical
compatible
same bus for up to 512K bits total memory
sion
- 10,000,000 E/W cycles guaranteed for High
- 100,000 E/W cycles guaranteed for a Stan-
- Commercial (C):
- Industrial (I)
- Automotive (E):
Endurance Block
dard Endurance Block
offers
a
64K 5.0V I
relocatable
-40 C to
-40 C to +125 C
0 C to
This document was created with FrameMaker 4 0 4
4K
+70 C
+85 C
bit
2
C Smart Serial EEPROM
2
C
block
of
PACKAGE TYPES
BLOCK DIAGRAM
options for E/W protection of critical data and/or code of
up to fifteen 4K blocks. Functional address lines allow
the connection of up to eight 24C65's on the same bus
for up to 512K bits contiguous EEPROM memory.
Advanced CMOS technology makes this device ideal
for low-power nonvolatile code and data applications.
The 24C65 is available in the standard 8-pin plastic DIP
and 8-pin surface mount SOIC package.
SDA
PDIP
Control
I/O
SOIC
Logic
I/O
Vcc
Vss
SCL
V
A0
A1
A2
SS
V
A0..A2
A0
A1
A2
SS
Memory
Control
Logic
1
2
3
4
1
2
3
4
XDEC
24C65
HV Generator
DS21058G-page 1
EEPROM ARRAY
8
7
6
5
8
7
6
9
Page Latches
Sense AMP
R/W Control
Cache
YDEC
V
NC
SCL
SDA
CC
V
NC
SCL
SDA
CC

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24C65-EP Summary of contents

Page 1

... E/W protection of critical data and/or code of block fifteen 4K blocks. Functional address lines allow the connection eight 24C65's on the same bus for up to 512K bits contiguous EEPROM memory. Advanced CMOS technology makes this device ideal for low-power nonvolatile code and data applications. ...

Page 2

... ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* V ...................................................................................7.0V CC All inputs and outputs w.r.t. V ............... -0. Storage temperature ..................................... -65˚C to +150˚C Ambient temp. with power applied ................ -65˚C to +125˚C Soldering temperature of leads (10 seconds) ............. +300˚C ESD protection on all pins *Notice: Stresses above those listed under “Maximum Ratings” ...

Page 3

... Schmitt trigger inputs which provide improved specification for standard operation HIGH DAT SU DAT 24C65 Units Remarks kHz (Note 1) ns (Note 1) ns After this period the first clock pulse is generated ns Only relevant for repeated START condition ...

Page 4

... NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24C65) must leave the data line HIGH to enable the master to generate the STOP condition. (D) ...

Page 5

... A control byte is the first byte received following the start condition from the master device. The control byte con- sists of a four bit control code, for the 24C65 this is set as 1010 binary for read and write operations. The next three bits of the control byte are the device select bits (A2, A1, A0) ...

Page 6

... FIGURE 4-2: PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 8- CONTROL BUS A BYTE ADDRESS (1) ACTIVITY: R MASTER T SDA LINE BUS C ACTIVITY: K FIGURE 4-3: CURRENT ADDRESS READ S T BUS ACTIVITY A MASTER SDA LINE BUS ACTIVITY FIGURE 4-4: RANDOM READ S T WORD CONTROL ...

Page 7

... The device select bits A2, A1, A0 can be used to expand the contiguous address space for up to 512K bits by adding up to eight 24C65's on the same bus. In this case, software can use A0 of the control byte as address bit A13 address bit A14, and A2 as address bit A15 ...

Page 8

... For example, if three blocks are to be protected, the third byte would be 10XX0011. After the third byte is sent to the device, it will acknowledge and a STOP bit is then sent by the master to complete the command. During a normal write sequence attempt is made ...

Page 9

... PIN DESCRIPTIONS 8.1 A0, A1, A2 Chip Address Inputs The A0..A2 inputs are used by the 24C65 for multiple device operation and conform to the two-wire bus stan- dard. The levels applied to these pins define the address block occupied by the device in the address map. A particular device is selected by transmitting the corresponding bits (A2, A1, A0) in the control byte (Figure 3-2 and Figure 8-1) ...

Page 10

... FIGURE 8-1: CONTROL SEQUENCE BIT ASSIGNMENTS Control Byte Address Byte Slave Device Address Select Bits Security Read S t Acknowledges from Device ...

Page 11

... Page 0 of cache written to page 3 of array. Write cycle is executed after every page is written. byte 2 byte 3 byte 4 • • • byte 7 page 3 24C65 cache page 7 • • • bytes 56-63 • • • page 7 array row n array row • • • ...

Page 12

... NOTES: DS21058G-page 12 1996 Microchip Technology Inc. ...

Page 13

... NOTES: 1996 Microchip Technology Inc. 24C65 DS21058G-page 13 ...

Page 14

... NOTES: DS21058G-page 14 1996 Microchip Technology Inc. ...

Page 15

... Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 24C65 – /P Package: Temperature Range: Device: 1996 Microchip Technology Inc Plastic DIP (300 mil Body Plastic SOIC (207 mil Body, EIAJ standard) Blank = 0˚ ...

Page 16

W ORLDWIDE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 ...

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