AT49BV1604-12UC ATMEL [ATMEL Corporation], AT49BV1604-12UC Datasheet - Page 5

• Manufacturer Part Number: AT49BV1604-12UC
• Description: 16-Megabit 1M x 16/2M x 8 3-volt Only Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49BV16X4(T) features DATA
polling to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte/word loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
DATA polling may begin at any time during the program
cycle. Please see “Status Bit Table” for more details.
T O G G L E B I T : I n a d d i t i o n t o D A T A p o l l i n g t h e
AT49BV16X4(T) provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
same memory plane will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2 which can be
used in conjunction with the toggle bit which is available on
I/O6. While a sector is erase suspended, a read or a pro-
gram operation from the suspended sector will result in the
I/O2 bit toggling. Please see status bit table for more
details.
RDY/BUSY: An open drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection
allows for OR-tying of several devices to the same
RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features
p r o t e c t a g a i n s t i n a d v e r t e n t p r o g r a m s t o t h e
AT49BV16X4(T) in the following ways: (a) V
V
ited. (b) V
V
ms (typical) before programming. (c) Program inhibit: hold-
ing any one of OE low, CE high or WE high inhibits pro-
gram cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE, and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to V
OUTPUT LEVELS: Output High Levels (V
V
must be tied to V
must be regulated to 2.0V ± 10% while V
lated to 2.7V - 3.0V (for minimum power).
CCQ
CC
CC
is below 1.8V (typical), the program function is inhib-
sense level, the device will automatically time out 10
- 0.2V (not V
CC
power on delay: once V
CC
CC
. For 1.8V - 2.2V output levels, V
). For 2.7V - 3.6V output levels, V
CC
+ 0.6V.
CC
CC
has reached the
OH
must be regu-
) are equal to
CC
sense: if
CCQ
CCQ
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