AT25320B ATMEL [ATMEL Corporation], AT25320B Datasheet - Page 9

• Manufacturer Part Number: AT25320B
• Description: SPI Serial EEPROMs 32K (4096 x 8) 64K (8192 x 8)
• Manufacturer: ATMEL [ATMEL Corporation]

8535B–SEEPR–7/08
Table 2-4.
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,
writes to the status register, including the block protect bits and the WPEN bit, and the block-pro-
tected sections in the memory array are disabled. Writes are only allowed to sections of the
memory that are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0” as
long as the WP pin is held low.
Table 2-5.
READ SEQUENCE (READ): Reading the AT25320B/640B via the Serial Output (SO) pin
requires the following sequence. After the CS line is pulled low to select a device, the read op-
code is transmitted via the SI line followed by the byte address to be read (A15
6). Upon completion, any data on the SI line will be ignored. The data (D7
address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be
driven high after the data comes out. The read sequence can be continued since the byte
address is automatically incremented and data will continue to be shifted out. When the highest
address is reached, the address counter will roll over to the lowest address allowing the entire
memory to be read in one continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25320B/640B, two separate instruc-
tions must be executed. First, the device must be write enabled via the WREN instruction.
Then a write (WRITE) instruction may be executed. Also, the address of the memory location(s)
to be programmed must be outside the protected address field location selected by the block
write protection level. During an internal write cycle, all commands will be ignored except the
RDSR instruction.
Level
WPEN
1(1/4)
2(1/2)
3(All)
X
X
0
0
1
1
0
Block Write Protect Bits
WPEN Operation
High
High
Low
Low
WP
X
X
Status Register Bits
BP1
0
0
1
1
WEN
0
1
0
1
0
1
BP0
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Blocks
0C00−0FFF
0800−0FFF
0000−0FFF
AT25320B
None
Array Addresses Protected
Unprotected
Protected
Protected
Protected
Writeable
Writeable
Writeable
Blocks
AT25320B/640B
–
D0) at the specified
1800−1FFF
1000−1FFF
0000−1FFF
AT25640B
–
A0, see
None
Protected
Writeable
Protected
Protected
Protected
Writeable
Register
Status
Table 2-
9