AT25DF041A-MU ATMEL [ATMEL Corporation], AT25DF041A-MU Datasheet
AT25DF041A-MU
Related parts for AT25DF041A-MU
AT25DF041A-MU Summary of contents
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... SOIC (150-mil and 200-mil wide) – 8-contact MLF ( mm) 1. Description The AT25DF041A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer-based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The ...
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... Specifically designed for use in 3-volt systems, the AT25DF041A supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing. ...
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... CC voltages may produce spurious results and should not be attempted. 8-SOIC Top View VCC HOLD SCK GND AT25DF041A Asserted State Low Low CC Low “Hold” whenever CC Figure 2-2. 8-MLF Top View CS VCC HOLD 2 7 ...
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... WP 4. Memory Array To provide the greatest flexibility, the memory array of the AT25DF041A can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into phys- ical sectors of various sizes, of which each sector can be individually protected from program and erase operations ...
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... – 003000h 4KB 002F – 002000h 4KB 001F – 001000h 4KB 000F – 000000h AT25DF041A Page Program Detail 1-256 Byte Page Program Page Address (02h Command) Range 256 Bytes 07F – 07F F 00h 256 Bytes 07F – ...
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... Device Operation The AT25DF041A is controlled by a set of instructions that are sent from a host controller, com- monly referred to as the SPI Master. The SPI Master communicates with the AT25DF041A via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO) ...
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... Use Write Status Register command 3Ch 0011 1100 3 05h 0000 0101 0 01h 0000 0001 0 9Fh 1001 1111 0 B9h 1011 1001 0 ABh 1010 1011 0 AT25DF041A Dummy Bytes Data Bytes ...
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... Figure 7-1. Read Array – 0Bh Opcode SCK OPCODE MSB HIGH-IMPEDANCE SO Figure 7-2. Read Array – 03h Opcode CS SCK SI MSB HIGH-IMPEDANCE SO AT25DF041A ADDRESS BITS A23- ...
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... If a programming error arises, it will be indicated by the EPE bit in the Status Register. 3668A–DFLASH–03/07 “Write Enable” on page 15 command description) to set the Write or t time to determine if the data bytes have finished programming AT25DF041A . PP “Protect Sector” ...
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... ADh or AFh must be clocked into the device. For the first program cycle, three address bytes must be clocked in after the opcode to designate the first byte location to program. After the address bytes have been clocked in, the byte of data to be programmed can be sent to the AT25DF041A 10 2 ...
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... The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly programming error arises, it will be indicated by the EPE bit in the Status Register. 3668A–DFLASH–03/07 AT25DF041A . For each program cycle time to determine if the byte has fin- ...
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... CS pin is deas- serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. AT25DF041A 12 Status Register Read ...
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... At BLKE Block Erase SCK OPCODE MSB HIGH-IMPEDANCE SO AT25DF041A ADDRESS BITS A23- MSB 31 A ...
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... The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-6. AT25DF041A 14 . CHPE time to determine if the device has finished erasing. At ...
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... CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. 3668A–DFLASH–03/07 Write Enable SCK OPCODE MSB HIGH-IMPEDANCE SO AT25DF041A ...
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... If the Sector Protection Registers are locked, then any attempts to issue the Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Reg- ister back to a logical “0” and return to the idle state once the CS pin has been deasserted. AT25DF041A 16 Write Disable ...
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... HIGH-IMPEDANCE SO Unprotect Sector SCK OPCODE MSB MSB HIGH-IMPEDANCE SO AT25DF041A ADDRESS BITS A23- Table 9-1 for Sector Protection ...
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... Global Unprotect, the same WP and SPRL conditions must be met but the system must write a logical “0” to bits and 2 of the Status Register. necessary for a Global Protect or Global Unprotect to be performed. AT25DF041A 18 page 26 for command execution details). The Write Status Register com- ...
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... SPRL bit can be changed back from a 1 since the WP ↕ pin is HIGH. To perform a Global Protect/Unprotect, the Write Status Register command must be issued again after the SPRL bit has been changed from AT25DF041A New SPRL Value ...
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... Figure 9-5. CS SCK SI SO AT25DF041A 20 for details on the Status Register format and what values can be Read Sector Protection Register – Output Data Sector Protection Register Value Sector Protection Register value is 0 (sector is unprotected). Sector Protection Register value is 1 (sector is protected). ...
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... Status Register. Tables 9-4 and 9-5 Table 9-4. Note: 3668A–DFLASH–03/07 detail the various protection and locking states of the device. Sector Protection Register States Sector Protection Register WP X (Don't Care) 1. “n” represents a sector number AT25DF041A Sector ( Unprotected 1 Protected ( ...
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... Table 9- AT25DF041A 22 Hardware and Software Locking SPRL Locking SPRL Change Allowed 0 Can be modified from Hardware 1 Locked Locked 0 Can be modified from Software 1 Can be modified from Locked Sector Protection Registers Unlocked and modifiable using the Protect and Unprotect Sector commands ...
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... Sector Protection Registers to determine which R sectors are protected. 10 Reserved for future use. All sectors are software protected (all Sector 11 Protection Registers are 1 – default). 0 Device is not write enabled (default Device is write enabled. 0 Device is ready Device is busy with an internal operation. AT25DF041A 23 ...
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... Protect Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have been protected, then the individual Sector Pro- tection Registers can be read with the Read Sector Protection Registers command to determine which sectors are in fact protected. AT25DF041A 24 3668A–DFLASH–03/07 ...
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... SI SO 3668A–DFLASH–03/ OPCODE MSB STATUS REGISTER DATA HIGH-IMPEDANCE MSB AT25DF041A STATUS REGISTER DATA MSB MSB 25 ...
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... WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. Table 10-2. Bit 7 SPRL Figure 10-2. Write Status Register AT25DF041A 26 page 18 for more details. Write Status Register Format Bit 6 ...
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... JEDEC Assigned Code Density Code Product Version Code AT25DF041A Hex Bit 0 Value Details 1Fh JEDEC Code: 0001 1111 (1Fh for Atmel) 1 Family Code: 010 (AT25/26DFxxx series) 44h Density Code: 00100 (4-Mbit) 0 Sub Code: 000 (Standard series) 01h ...
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... The Deep Power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-down mode. AT25DF041A ...
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... Standby Mode Current Deep Power-Down Mode Current and return to the standby mode. After the device RDPD SCK OPCODE MSB HIGH-IMPEDANCE SO Active Current I CC Deep Power-Down Mode Current AT25DF041A t EDPD t RDPD Standby Mode Current 29 ...
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... If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state. Figure 11-4. Hold Mode CS SCK HOLD AT25DF041A 30 Hold Hold Hold 3668A–DFLASH–03/07 ...
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... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT25DF041A -40°C to 85°C 2.7V to 3.6V Min Typ Max 25 ...
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... Chip Select High to Standby Mode RDPD Notes: 1. Not 100% tested (value guaranteed by design and characterization load at 70 MHz load at 66 MHz. 3. Only applicable as a constraint for the Write Status Register command when SPRL = 1 AT25DF041A 32 Min Max Units 70 MHz 33 MHz 6 ...
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... Input Test Waveforms and Measurement Levels < (10 12.8 Output Test Load 3668A–DFLASH–03/07 Min 4 Kbytes 32 Kbytes 64 Kbytes Min 50 1.5 2.4V AC 1.5V DRIVING LEVELS 0.45V DEVICE UNDER TEST AT25DF041A Typ Max Units 1 µs 50 200 250 600 ms 400 950 3 7 sec 200 ns Max Units µ ...
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... Figure 13-1. Serial Input Timing CS t CSLS SCK MSB HIGH-IMPEDANCE SO Figure 13-2. Serial Output Timing CS SCK Figure 13-3. HOLD Timing – Serial Input CS SCK HOLD SI HIGH-IMPEDANCE SO AT25DF041A 34 t CSLH t t SCKH SCKL t DH LSB HHH HLS t HLH t CSH t ...
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... Figure 13-5. WP Timing for Write Status Register Command When SPRL = WPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER OPCODE HIGH-IMPEDANCE SO 3668A–DFLASH–03/07 t HLS t HLH t t HLQZ HHQX LSB OF WRITE STATUS REGISTER DATA BYTE AT25DF041A t HHS WPH MSB MSB OF NEXT OPCODE 35 ...
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... Ordering Code SCK AT25DF041A-SSU 70 AT25DF041A-SU AT25DF041A-MU 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.209” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8M1-A 8-contact Very Thin Micro Lead-frame Package (MLF) ...
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... Colorado Springs, CO 80906 R 3668A–DFLASH–03/ TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) AT25DF041A Ø Ø END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A1 0.10 – ...
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... It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. 5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. 2325 Orchard Parkway San Jose, CA 95131 R AT25DF041A TOP VIEW ...
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... San Jose, CA 95131 R 3668A–DFLASH–03/ Pin 1 ID TOP VIEW 0.45 Pin #1 Notch (0. TITLE 8M1-A, 8-pad 1.00 mm Body, Very Thin Dual Flat Package No Lead (MLF) AT25DF041A SIDE VIEW A3 A1 0.08 C COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A – 0.85 1.00 A1 – – 0. ...
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... Revision History Revision Level – Release Date A – March 2007 AT25DF041A 40 History Initial Release 3668A–DFLASH–03/07 ...
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... Atmel Corporation. All rights reserved. Atmel istered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 ...