AT49F010-12JI ATMEL [ATMEL Corporation], AT49F010-12JI Datasheet - Page 3

• Manufacturer Part Number: AT49F010-12JI
• Description: 1-Megabit 128K x 8 5-volt Only CMOS Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

Absolute Maximum Ratings*
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F010/HF010 features DATA
polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA
polling may begin at any time during the program cycle.
Command Definition (in Hex)
Notes: 1. The 8K byte boot sector has the address range 00000H to 01FFFH.
Command
Sequence
Read
Chip Erase
Byte
Program
Boot Block
Lockout
Product ID
Entry
Product ID
Exit
Product ID
Exit
Temperature Under Bias................. -55 C to +125 C
Storage Temperature...................... -65 C to +150 C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
(2)
(2)
2. Either one of the Product ID exit commands can be used.
(1)
Cycles
Bus
1
6
4
6
3
3
1
XXXX
Addr
Addr
5555
5555
5555
5555
5555
1st Bus
Cycle
D
Data
AA
AA
AA
AA
AA
F0
OUT
2AAA
2AAA
2AAA
2AAA
2AAA
Addr
2nd Bus
Cycle
CC
Data
+ 0.6V
55
55
55
55
55
5555
5555
5555
5555
5555
Addr
3rd Bus
Cycle
T O G G L E B I T : I n a d d i t i o n t o DATA p o l l i n g t h e
AT49F010/HF010 provides another method for determin-
ing the end of a program or erase cycle. During a program
or erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
p r o t e c t a g a i n s t i n a d v e r t e n t p r o g r a m s t o t h e
AT49F010/HF010 in the following ways: (a) V
V
ited. (b) Program inhibit: holding any one of OE low, CE
high or WE high inhibits program cycles. (c) Noise filter:
Pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
CC
Data
A0
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
80
80
90
F0
is below 3.8V (typical), the program function is inhib-
5555
5555
Addr
Addr
4th Bus
Cycle
Data
D
AA
AA
IN
AT49F010/HF010
2AAA
2AAA
Addr
5th Bus
Cycle
Data
55
55
Addr
5555
5555
6th Bus
CC
Cycle
sense: if
Data
10
40
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