IS43R16800A-6T ISSI [Integrated Silicon Solution, Inc], IS43R16800A-6T Datasheet - Page 24

• Manufacturer Part Number: IS43R16800A-6T
• Description: 8Meg x 16 128-MBIT DDR SDRAM
• Manufacturer: ISSI [Integrated Silicon Solution, Inc]

IS43R16800A-6
24
Write operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4,
or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by
the column address, the bank select address which are loaded via the A0 to A11, BA0 to BA1 pins in the cycle when
the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst
operation. tWPRE prior to the first rising edge of the DQS should be set to Low and tWPST after the last falling edge
of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last low
period of DQS is referred as write postamble.
Command
DQS
DQ
Address
CL = 2.5
/CK
CK
CL = 2
Command
NOP
DQS
DQS
t0
/CK
DQ
DQ
CK
Row
ACT
t1
READ
BL = 2
BL = 4
BL = 8
t0
NOP
tRCD
t0.5
tRPRE
tAC,tDQSCK
Read Operation (/CAS Latency)
tWPRES
t1
tRPRE
Column
WRITE
tn tn+0.5 tn+1
tAC,tDQSCK
t1.5
Write Operation
tWPRE
t2
in0
in0
in0
out0
in1
in1
in1
t2.5
Integrated Silicon Solution, Inc. — 1-800-379-4774
out1
out0
NOP
in2
in2
tn+2
t3
in3
in3
out2 out3
out1
tWPST
t3.5
in4 in5
tn+3
out2
t4
NOP
tRPST
out3
in6
t4.5
tn+4
tRPST
in7
t5
tn+5
t5.5
BL: Burst length
ISSI
VTT
VTT
VTT
VTT
04/04/06
Rev. 00A
®