M95128-MN3TP/P STMICROELECTRONICS [STMicroelectronics], M95128-MN3TP/P Datasheet - Page 23

• Manufacturer Part Number: M95128-MN3TP/P
• Description: 128 Kbit serial SPI bus EEPROM with high speed clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M95128, M95128-W, M95128-R
6
7
Delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 12. Bus master and memory devices on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 12
bus. Only one memory device is selected at a time, so only one memory device drives the
Serial Data Output (Q) line at a time, the other memory devices are high impedance.
The pull-up resistor R (represented in
bus master leaves the S line in the high impedance state.
SPI Interface with
CS3
(CPOL, CPHA) =
(0, 0) or (1, 1)
Bus master
CS2 CS1
shows an example of three memory devices connected to an MCU, on an SPI
SDO
SDI
SCK
R
R
C Q D
S
Doc ID 5798 Rev 13
SPI memory
device
W
Figure
V
CC
HOLD
V
SS
12) ensures that a device is not selected if the
R
C Q D
S
SPI memory
device
W
V
CC
HOLD
V
SS
R
C Q D
S
SPI memory
Delivery state
device
W
V
CC
HOLD
AI12304c
23/44
V
V
SS
V
CC
SS