M24C02-125 STMICROELECTRONICS [STMicroelectronics], M24C02-125 Datasheet - Page 17

• Manufacturer Part Number: M24C02-125
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24C16-125 M24C08-125 M24C04-125 M24C02-125
3.7
3.7.1
Figure 9.
1. The seven most significant bits of the device select code of a Random Read (in the 1
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
The device has an internal address counter which is incremented each time a byte is read.
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
be identical.
9) but without sending a Stop condition. Then, the bus master sends another Start
Current
Address
Read
Random
Address
Read
Sequentila
Current
Read
Sequential
Random
Read
Read mode sequences
Dev select *
Dev select *
Dev select
Dev select
ACK
Doc ID 022564 Rev 1
Data out N
R/W
R/W
R/W
R/W
ACK
ACK
ACK
ACK
NO ACK
Byte address
Byte address
Data out 1
Data out
NO ACK
ACK
ACK
ACK
Dev select *
Dev select *
ACK
ACK
ACK
R/W
R/W
Data out N
Data out 1
Data out
st
and 3
Device operation
NO ACK
NO ACK
rd
ACK
AI01942b
bytes) must
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