M34E02-FDW1 STMICROELECTRONICS [STMicroelectronics], M34E02-FDW1 Datasheet
M34E02-FDW1
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M34E02-FDW1 Summary of contents
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... Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Protection More than 1 Million Erase/Write Cycles More than 40 Year Data Retention November 2004 2 Kbit Serial I²C Bus EEPROM Serial Presence Detect for DDR2 DIMMs Figure 1. Packages M34E02 UFDFPN8 (MB) 2x3mm² (MLP) TSSOP8 (DW) 4.4x3mm² 1/23 ...
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... M34E02 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TSSOP and MLP Connections (Top View Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Power On Reset: V Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 CC SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Serial Clock (SCL Serial Data (SDA Chip Enable (E0, E1, E2 Write Control (WC Figure 4 ...
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... USE WITHIN A DDR2 DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. DRAM DIMM Connections Programming the M34E02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DDR2 DIMM Isolated DDR2 DIMM Inserted in the Application Mother Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Acknowledge when Writing Data or Defining the Write-protection (Instructions with R/W bit= Table 6. Acknowledge when Reading the Write Protection (Instructions with R/W bit=1 Figure 11 ...
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... M34E02 SUMMARY DESCRIPTION The M34E02 Kbit serial EEPROM memory able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual interline memory modules) with Serial Presence Detect. All the information concerning ...
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... Protection Register. BUS fc = 100kHz fc = 400kHz 100 C BUS (pF establish the Device Se for Bus SDA MASTER SCL C BUS 1000 M34E02 voltage, C BUS AI01665 5/23 ...
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... M34E02 2 Figure Bus Protocol SCL SDA START Condition SCL MSB SDA START Condition 1 SCL MSB SDA Table 2. Device Select Code Chip Enable Signals Memory Area Select Code 2 (two arrays) Set Write Protection (SWP) Clear Write Protection (CWP) Permanently Set Write ...
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... C bus. Each one is given a unique 3-bit th bit is the Read/Write bit (RW). This bit is th Initial Sequence START, Device Select START, Device Select Address reSTART, Device Select Similar to Current or Random Address Read START, Device Select START, Device Select M34E02 bit time. If the 7/23 ...
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... This write-protection cannot be cleared by any in- struction power-cycling the device, and re- gardless the state of Write Control (WC). Also, once the PSWP instruction has been successfully executed, the M34E02 no longer acknowledges any instruction (with a Device Type Identifier of 0110) to access the write-protection settings. CONTROL ...
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... NoAck, and the locations are not modified. After each byte is transferred, the in- ternal byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. M34E02 ACK ACK DATA IN 2 AI01941 9/23 ...
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... M34E02 Figure 9. Write Cycle Polling Flowchart using ACK First byte of instruction with already decoded by the device NO ReSTART STOP Minimizing System Delays by Polling On ACK During the internal Write cycle, the device discon- nects itself from the bus, and writes a copy of the data from its internal latches to the memory cells ...
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... Select Code with the RW bit set to 1. The de- vice acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master ter- minates the transfer with a Stop condition, as shown in Figure 10, without acknowledging the byte. M34E02 ACK NO ACK DATA OUT R/W ACK NO ACK ...
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... The pull-up resistors needed for 2 normal behavior of the I C bus are connected on 2 the I C bus of the mother-board (as shown in Figure 11). The Write Control (WC) of the M34E02 can be left unconnected. However, connecting recommended, to maintain full read and write access. 12/23 Table 4. DRAM DIMM Connections DIMM Position 0 ...
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... Not Ack significant Ack Address Ack Address NoAck Not significant NoAck Not significant Ack Not significant Ack Not significant Ack Not significant M34E02 Ack Data Byte Ack Not NoAck NoAck significant Ack Data NoAck Not NoAck NoAck significant Not Ack Ack ...
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... M34E02 Figure 11. Serial Presence Detect Block Diagram DIMM Position 7 E2 DIMM Position DIMM Position DIMM Position DIMM Position DIMM Position DIMM Position DIMM Position 0 E2 AI01937 Note: 1. E0, E1 and E2 are wired at each DIMM socket in a binary sequence for a maximum of 8 devices. ...
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... Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 1 E0 Others 2 , R2=500 ) M34E02 Min. Max. Unit –65 150 °C 1 °C See note –0.50 10.0 V – ...
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... M34E02 DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests performed under the Measure- Table 8. Operating Conditions Symbol V Supply Voltage ...
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... CC ± 3. 1.7V 0.5 CC 0.3 V –0. 3.6V 0 1.7V 0.2 Min. Max. 100 4000 4700 20 300 250 0 200 200 3500 4700 4000 4000 4700 10 M34E02 1 Unit µA µ µA µ Unit kHz 17/23 ...
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... M34E02 Figure 13. AC Waveforms tCHCL SCL tDLCL SDA In tCHDX START Condition SCL SDA In tCHDH STOP Condition SCL tCLQV SDA Out 18/23 tCLCH tCLDX tDXCX SDA Change SDA Input tW Write Cycle tCLQX Data Valid tCHDH tDHDL STOP START Condition Condition tCHDX START Condition ...
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... Max. 0.50 0.60 0.00 0.05 0.20 0.30 1.55 1.65 0.05 0.15 0.25 – – 0.40 0.50 0.15 0. UFDFPN- must not be allowed to be connected to SS inches Typ. Min. 0.022 0.020 0.000 0.010 0.008 0.079 0.061 0.118 0.006 0.020 – 0.018 0.016 0.012 8 M34E02 Max. 0.024 0.002 0.012 0.065 0.002 0.010 – 0.020 0.006 19/23 ...
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... M34E02 Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline A CP Notes: 1. Drawing is not to scale. Table 14. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data Symbol Typ 1.000 3.000 e 0.650 E 6.400 E1 4.400 L 0.600 L1 1.000 N 20/ ...
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... Plating Technology blank = Standard SnPb plating P = Lead-Free and RoHS compliant G = Lead-Free, RoHS compliant, Sb For a list of available options (speed, package, etc.) or for further information on any aspect of this M34E02 – O -free and TBBA-free 2 3 device, please contact your nearest ST Sales Of- fice. M34E02 21/23 ...
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... M34E02 REVISION HISTORY Table 16. Revision History Date Rev. 13-Nov-2003 1.0 First release TSSOP8 4.4x3 package replaces TSSOP8 3x3 (MSOP8) package. Correction to sentence in 01-Dec-2003 1.1 “Setting the Write Protection”. Correction to specification of t Always NoACK after Address and Data bytes in Table 6. Improvement in V Absolute Maximum Ratings table. I 29-Mar-2004 1 ...
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