M95080-DW3G/G STMICROELECTRONICS [STMicroelectronics], M95080-DW3G/G Datasheet - Page 16

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M95080-DW3G/G

Manufacturer Part Number
M95080-DW3G/G
Description
16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
Instructions
6
6.1
16/50
Instructions
Each instruction starts with a single-byte code, as summarized in
If an invalid instruction is sent (one not contained in
deselects itself.
Table 4.
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 7.
WREN
WRDI
RDSR
WRSR
READ
WRITE
Instruction
Instruction set
Figure
Write Enable (WREN) sequence
S
C
D
Q
7., to send this instruction to the device, Chip Select (S) is driven low,
Write Enable
Write Disable
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
Doc ID 8028 Rev 10
Description
High Impedance
0
1
2
Instruction
3
4
5
Table
6
7
4.), the device automatically
Instruction format
AI02281E
Table 4.
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
M95160-x, M95080-x

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