M24128-BR STMICROELECTRONICS [STMicroelectronics], M24128-BR Datasheet - Page 17

• Manufacturer Part Number: M24128-BR
• Description: 128 Kbit, 64 Kbit and 32 Kbit serial I2C bus EEPROM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24128, M24C64, M24C32
4.9
Figure 9.
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
shown in
sequence can be used by the bus master.
The sequence, as shown in
First byte of instruction
with RW = 0 already
decoded by the device
–
–
–
Table 17
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a Device Select Code
(the first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned
and the bus master goes back to Step 1. If the device has terminated the internal
Write cycle, it responds with an Ack, indicating that the device is ready to receive
the second part of the instruction (the first byte of this instruction having been sent
during Step 1).
Write cycle polling flowchart using ACK
ReSTART
and
STOP
Table
NO
Figure
18, but the typical time is shorter. To make use of this, a polling
NO
DEVICE SELECT
START Condition
WRITE Cycle
Addressing the
with RW = 0
in Progress
Operation is
Returned
9, is:
Memory
ACK
Next
YES
WRITE Operation
WRITE Operation
DATA for the
Continue the
YES
NO
and Receive ACK
Send Address
Condition
START
Random READ Operation
DEVICE SELECT
Continue the
with RW = 1
YES
Device operation
AI01847C
w
) is
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