M24128-BN5T STMICROELECTRONICS [STMicroelectronics], M24128-BN5T Datasheet - Page 8

• Manufacturer Part Number: M24128-BN5T
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24256, M24128
Figure 8. Read Mode Sequences
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
Read Operations
Read operations are performed independently of
the state of the WC pin.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, the mas-
ter sends another START condition, and repeats
8/17
minated the internal write cycle, it responds with
an Ack, indicating that the memory is ready to
receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
DEV SEL *
DEV SEL *
DEV SEL
DEV SEL
ACK
DATA OUT N
R/W
R/W
R/W
ACK
ACK
ACK
ACK
R/W
NO ACK
DATA OUT 1
BYTE ADDR
BYTE ADDR
DATA OUT
NO ACK
ACK
ACK
ACK
BYTE ADDR
BYTE ADDR
the Device Select Code, with the RW bit set to ‘1’.
The memory acknowledges this, and outputs the
contents of the addressed byte. The master must
not acknowledge the byte output, and terminates
the transfer with a STOP condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to ‘1’. The memory acknowl-
edges this, and outputs the byte addressed by the
internal address counter. The counter is then in-
ACK
ACK
ACK
DATA OUT N
DEV SEL *
DEV SEL *
st
and 4
NO ACK
R/W
ACK
ACK
R/W
th
bytes) must be identical.
DATA OUT 1
DATA OUT
NO ACK
ACK
AI01105C