M24128-BR3BN6T STMICROELECTRONICS [STMicroelectronics], M24128-BR3BN6T Datasheet - Page 8

• Manufacturer Part Number: M24128-BR3BN6T
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24256-B, M24128-B
Figure 7. Write Cycle Polling Flowchart using ACK
internal address counter. The counter is then in-
cremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8, with-
out acknowledging the byte output.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from
memory address 00h.
8/19
First byte of instruction
with RW = 0 already
decoded by M24xxx
ReSTART
STOP
NO
NO
START Condition
DEVICE SELECT
WRITE Cycle
Addressing the
in Progress
with RW = 0
Operation is
Returned
Memory
ACK
Next
YES
WRITE Operation
Proceed
YES
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
Byte Address
Send
Random Address
READ Operation
Proceed
AI01847
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