M24256-BHR STMICROELECTRONICS [STMicroelectronics], M24256-BHR Datasheet - Page 6

• Manufacturer Part Number: M24256-BHR
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Description
1
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Description
The M24512-W, M24512-R, M24512-HR, M24256-BW, M24256-BR and M24256-BHR
devices are I
are organized as 64 Kb × 8 bits and 32 Kb × 8 bits, respectively.
I
devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I
bus definition.
The device behaves as a slave in the I
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in
When writing data to the memory, the device inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Figure 1.
Table 1.
2
E0, E1, E2
SDA
SCL
WC
V
V
C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The
CC
SS
Signal name
2
Logic diagram
Signal names
C-compatible electrically erasable programmable memories (EEPROM). They
Table
E0-E2
SCL
WC
Chip Enable
Serial Data
Serial Clock
Write Control
Supply voltage
Ground
2), terminated by an acknowledge bit.
3
2
C protocol, with all memory operations synchronized
M24256-BHR
V CC
M24256-BW
M24512-HR
M24256-BR
M24512-W
V SS
M24512-R
Function
SDA
AI02275d
Input
Inputs
I/O
Input
M24512-x, M24256-Bx
Direction
th
bit
2
C