M95256-CS3G/A STMICROELECTRONICS [STMicroelectronics], M95256-CS3G/A Datasheet - Page 15

• Manufacturer Part Number: M95256-CS3G/A
• Description: 256 Kbit serial SPI bus EEPROM with high-speed clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M95256-DR, M95256, M95256-W, M95256-R
5.1
5.2
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven
high.
Figure 6.
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
●
●
●
Figure 7.
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion
Figure
Write Enable (WREN) sequence
Figure
Write Disable (WRDI) sequence
S
C
D
Q
6, to send this instruction to the device, Chip Select (S) is driven low,
7, to send this instruction to the device, Chip Select (S) is driven low,
S
C
D
Q
Doc ID 12276 Rev 11
High Impedance
0
High Impedance
0
1
1
2
2
Instruction
Instruction
3
3
4
4
5
5
6
6
7
7
AI02281E
AI03750D
Instructions
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