CY62128B CYPRESS [Cypress Semiconductor], CY62128B Datasheet - Page 5

no-image

CY62128B

Manufacturer Part Number
CY62128B
Description
128K x 8 Static RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62128BLL
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
CY62128BLL-55SC
Manufacturer:
CYPRESS
Quantity:
4
Part Number:
CY62128BLL-55SI
Manufacturer:
CY
Quantity:
3 000
Company:
Part Number:
CY62128BLL-55SI
Quantity:
11
Part Number:
CY62128BLL-55SXC
Manufacturer:
CYP
Quantity:
2 340
Part Number:
CY62128BLL-55SXI
Manufacturer:
CYP
Quantity:
5 120
Part Number:
CY62128BLL-55SXIT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
CY62128BLL-55ZAI
Manufacturer:
CYP
Quantity:
20 000
Company:
Part Number:
CY62128BLL-55ZAIT
Quantity:
1 500
Part Number:
CY62128BLL-55ZC
Manufacturer:
CYP
Quantity:
5 120
Part Number:
CY62128BLL-70SC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Company:
Part Number:
CY62128BLL-70SC
Quantity:
20
Part Number:
CY62128BLL-70SCT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document #: 38-05300 Rev. *C
Switching Characteristics
Switching Waveforms
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Read Cycle No.1
Notes:
10. The internal write time of the memory is defined by the overlap of CE
11. No input may exceed V
12. Device is continuously selected. OE, CE
13. WE is HIGH for read cycle.
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
8. t
9. At any given temperature and voltage condition, t
Parameter
DATA OUT
ADDRESS
I
the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
OL
HZOE
/I
OH
, t
and 100-pF load capacitance.
HZCE
, and t
[10]
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE
CE
CE
CE
Write Cycle Time
CE
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[12, 13]
1
1
1
1
1
1
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
CC
LOW to Data Valid, CE
LOW to Low Z, CE
HIGH to High Z, CE
LOW to Power-up, CE
HIGH to Power-down, CE
LOW to Write End, CE
+ 0.5V.
PREVIOUS DATA VALID
[7]
1
= V
Over the Operating Range
[9]
[8, 9]
[8, 9]
IL
, CE
2
t
Description
OHA
HZCE
2
2
HIGH to Low Z
= V
LOW to High Z
2
2
2
is less than t
IH
HIGH to Power-up
HIGH to Write End
HIGH to Data Valid
.
2
LOW to Power-down
t
AA
LZCE
1
LOW, CE
[9]
, t
[8, 9]
HZOE
is less than t
2
HIGH, and WE LOW. CE
t
RC
LZOE
, and t
HZWE
Min.
55
55
45
45
45
25
62128B-55
5
0
0
5
0
0
0
5
1
is less than t
and WE must be LOW and CE
Max.
55
55
20
20
20
55
20
LZWE
DATA VALID
for any given device.
Min.
70
70
60
60
50
30
62128B-70
5
0
0
5
0
0
0
5
2
HIGH to initiate a write, and
CY62128B
Max.
70
70
35
25
25
70
25
MoBL
Page 5 of 11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Related parts for CY62128B