M28W320EB-ZB STMICROELECTRONICS [STMicroelectronics], M28W320EB-ZB Datasheet - Page 9

• Manufacturer Part Number: M28W320EB-ZB
• Description: 32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or data to be programmed during a Write Bus op-
eration.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at V
mode. When Chip Enable is at V
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable controls
data outputs during the Bus Read operation of the
memory.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable, E, or Write En-
able, W, whichever occurs first.
Write Protect (WP). Write Protect is an input to
protect or unprotect the two lockable parameter
blocks. When Write Protect is at V
blocks are protected and Program or Erase oper-
ations are not possible. When Write Protect is at
V
be programmed or erased (refer to Table 5, Mem-
ory Blocks Protection Truth).
Reset (RP). The Reset input provides a hard-
ware reset of the memory. When Reset is at V
the memory is in reset mode: the outputs are high
impedance and the current consumption is mini-
mized. When Reset is at V
IH
, the lockable blocks are unprotected and can
IL
and Reset is at V
IH
IH
the device is in active
, the device is in nor-
IH
IL
the memory is
, the lockable
IL
,
mal operation. Exiting reset mode the device
enters read array mode, but a negative transition
of Chip Enable or a change of the address is re-
quired to ensure valid data outputs.
V
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
V
power supply to the I/O pins and enables all Out-
puts to be powered independently from V
can be tied to V
V
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin. The Supply Voltage V
Program Supply Voltage V
any order.
If V
V
age lower than V
against program or erase, while V
ables these functions (see Table 12, DC Charac-
teristics for the relevant values). V
sampled at the beginning of a Program or Erase;
a change in its value after the operation has start-
ed does not have any effect on Program or Erase,
however for Double or Quadruple Word Program
the results are uncertain.
If V
power supply pin. In this condition V
stable until the Program/Erase algorithm is com-
pleted (see Table 14 and 15).
V
measurements.
Note: Each device in a system should have
V
pacitor close to the pin. See Figure 7, AC Mea-
surement Load Circuit. The PCB trace widths
should be sufficient to carry the required V
Program and Erase currents.
PP
SS
DD,
DD
DDQ
PP
PP
PP
Ground. V
is seen as a control input. In this case a volt-
V
Program Supply Voltage. V
Supply Voltage. V
DDQ
Supply Voltage. V
is kept in a low voltage range (0V to 3.6V)
is in the range 11.4V to 12.6V it acts as a
and V
M28W320EBT, M28W320EBB
DD
PPLK
SS
PP
or can use a separate supply.
is the reference for all voltage
decoupled with a 0.1µF ca-
gives an absolute protection
DD
PP
DDQ
provides the power
can be applied in
provides
PP
PP
PP
> V
PP
DD
is both a
DD
must be
and the
PP1
is only
. V
DDQ
9/45
the
en-
PP