CY62256V-55RZC CYPRESS [Cypress Semiconductor], CY62256V-55RZC Datasheet

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CY62256V-55RZC

Manufacturer Part Number
CY62256V-55RZC
Description
32K x 8 Static RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Cypress Semiconductor Corporation
Document #: 38-05057 Rev. *D
Features
• Temperature Ranges
• Speed: 70 ns and 100 ns
• Low voltage range:
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Package available in a standard 450-mil-wide (300-mil
Note:
1.
Logic Block Diagram
body width) 28-lead narrow SOIC, 28-lead TSOP-1, and
reverse 28-lead TSOP-1 package
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
— CY62256V (2.7V–3.6V)
— CY62256V25 (2.3V–2.7V)
For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
CE
WE
OE
A
A
A
A
A
A
A
A
A
10
9
8
7
6
5
4
3
2
3901 North First Street
INPUTBUFFER
512 × 512
DECODER
COLUMN
ARRA Y
Functional Description
The CY62256V family is composed of two high-performance
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state
drivers. These devices have an automatic power-down
feature, reducing the power consumption by over 99% when
deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
addressed by the address present on the address pins (A
through A
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
POWER
DOWN
0
through I/O
256K (32K x 8) Static RAM
14
). Reading the device is accomplished by selecting
San Jose
7
) is written into the memory location
CA 95134
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
[1]
0
1
2
3
4
5
6
7
Revised June 28, 2004
CY62256V
408-943-2600
0

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CY62256V-55RZC Summary of contents

Page 1

... Document #: 38-05057 Rev. *D 256K (32K x 8) Static RAM Functional Description The CY62256V family is composed of two high-performance CMOS static RAM’s organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers ...

Page 2

... OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins GND. Ground for the device Vcc. Power supply for the device CY62256V Power Dissipation Operating, I (mA) Standby, I ...

Page 3

... C 2.3V to 2.7V CY62256V-70 [2] Min. Typ. Max. = 2.7V 2 2.7V 0 +0.3V –0.5 0.8 –1 +1 -10 +10 –1 +1 -10 + 100 300 0 130 CY62256V25-100 [2] Min. Typ. Max. Vcc=2.3V 2 Vcc= 2.3V 0.4 1.7 Vcc + 0.3V –0.3 0.7 –1 +1 –1 +1 Page Unit µA µA µA µA mA µA Unit µA ...

Page 4

... 10% R2 GND < Equivalent to: THÉ VENIN EQUIVALENT R th OUTPUT 3.3V 1100 1500 645 1.750 CY62256V CY62256V25-100 [2] Min. Typ. Com’l, Ind’l 9 MAX Com’l, Ind’l 75 MAX Com’l 0.1 Ind’l Max ALL INPUT PULSES 90% 90% 10% < ...

Page 5

... CE > V – 0.3V > V – 0. < 0. DATA RETENTION MODE 1.8V V > 1. CDR Test Conditions Still Air, soldered × 4.5 inch, [6] four-layer printed circuit board CY62256V [2] Min. Typ. Max. 1.4 Com’l 0.1 3 Ind’l 6 Auto 1. SOIC TSOPI RTSOPI 68 ...

Page 6

... Description [8] [8, 9] [8] [8, 9] [ less than less than t HZCE LZCE HZOE = ( Test Loads. Transition is measured ± 200 mV from steady-state voltage. L HZWE CY62256V CY62256V-70 CY62256V25-100 Min. Max. Min. Max. 70 100 70 100 100 ...

Page 7

... WE is HIGH for read cycle. Document #: 38-05057 Rev OHA ACE t DOE t LZOE 50% [10, 15, 16 PWE t SD DATA CY62256V DATA VALID t HZOE t HZCE DATA VALID VALID HIGH IMPEDANCE ICC ISB Page ...

Page 8

... If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05057 Rev. *D [10, 15, 16 DATA [11, 16 DATA t HZWE CY62256V SCE VALID VALID IN t LZWE ...

Page 9

... V = 2.5V CC 1.2 1.0 0.8 0.6 − 3.6 AMBIENT TEMPERATURE (°C) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE -14 - 25° 0.5 1.5 0.0 1.0 OUTPUT VOLTAGE (V) CY62256V STANDBY CURRENT vs. AMBIENT TEMPERATURE 3.0 = 3.0V 2.5 2.0 1.5 1.0 0 0.0 -0.5 − 125 AMBIENT TEMPERATURE (°C) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 3. 2 25°C ...

Page 10

... H L Data Out Data High-Z Ordering Information Speed (ns) Ordering Code 70 CY62256VLL-70SNC CY62256VLL-70ZC CY62256VLL-70ZI CY62256VLL -70SNI CY62256VLL-70ZRI CY62256VLL-70SNE CY62256VLL-70ZE CY62256VLL-70ZRE 100 CY62256V25LL-100ZC Document #: 38-05057 Rev. *D (continued) 600 800 1000 Inputs/Outputs Deselect/Power-down Read Write Deselect, Output Disabled Package Name SN28 ...

Page 11

... Package Diagrams 28-lead Thin Small Outline Package Type 1 (8 × 13.4 mm) Z28 Document #: 38-05057 Rev. *D 28-lead (300-mil) SNC (Narrow Body) SN28 CY62256V 51-85092-*B 51-85071-*G Page ...

Page 12

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62256V 51-85074-*F ...

Page 13

... Document Title: CY62256V 256K (32K x 8) Static RAM Document Number: 38-05057 REV. ECN NO. Issue Date ** 107248 09/10/01 *A 111445 11/01/01 *B 115229 05/23/02 *C 116507 09/04/02 *D 239134 See ECN Document #: 38-05057 Rev. *D Orig. of Change SZV Changed from spec number: 38-00519 to 38-05057 MGN Removed obsolete parts. Change to standard format ...

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