M27C160-100B6 STMICROELECTRONICS [STMicroelectronics], M27C160-100B6 Datasheet - Page 4

• Manufacturer Part Number: M27C160-100B6
• Description: 16 Mbit 2Mb x8 or 1Mb x16 UV EPROM and OTP EPROM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M27C160
Table 5. AC Measurement Conditions
Figure 5. AC Testing Input Output Waveform
Table 6. Capacitance
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION
The operating modes of the M27C160 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V
Electronic Signature.
Read Mode
The M27C160 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTEV
is at V
and the Q15A–1 pin is used for Q15 Data Output.
When the BYTEV
ganisation is selected and the Q15A–1 pin is used
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at V
4/19
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
High Speed
Standard
Symbol
2.4V
0.4V
C
3V
0V
C
IH
OUT
IN
the Word-wide organisation is selected
Input Capacitance (except BYTEV
Input Capacitance (BYTEV
Output Capacitance
PP
pin is at V
(1)
PP
(T
PP
and 12V on A9 for the
A
pin. When BYTEV
= 25 °C, f = 1 MHz)
Parameter
IL
the Byte-wide or-
PP
1.5V
2.0V
0.8V
AI01822
)
IL
the
PP
PP
)
High Speed
0 to 3V
1.5V
Figure 6. AC Testing Load Circuit
lower 8 bits of the 16 bit data are selected and with
A–1 at V
selected.
The M27C160 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte- wide organisation must be selected.
Chip Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t
from E to output (t
output after a delay of t
of G, assuming that E has been low and the ad-
dresses have been stable for at least t
10ns
Test Condition
C L = 30pF for High Speed
C L = 100pF for Standard
C L includes JIG capacitance
V
DEVICE
V
V
UNDER
OUT
TEST
IN
IN
IH
= 0V
= 0V
= 0V
the upper 8 bits of the 16 bit data are
ELQV
AVQV
1.3V
Min
GLQV
). Data is available at the
) is equal to the delay
1N914
3.3k
0.4V to 2.4V
0.8V and 2V
C L
from the falling edge
Standard
20ns
Max
120
10
12
AVQV
OUT
AI01823B
-t
Unit
GLQV
pF
pF
pF
.