NAND04GA3C2A STMICROELECTRONICS [STMicroelectronics], NAND04GA3C2A Datasheet - Page 23

• Manufacturer Part Number: NAND04GA3C2A
• Description: 4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

NAND04GA3C2A, NAND04GW3C2A
Figure 9.
6.8
RB
I/O
Row Add 1,2,3
Code
Cmd
80h
Random Data Input During Sequential Data Input
Block Erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to
1.
2.
3.
The operation is initiated on the rising edge of write Enable, W, after the confirm command
is issued. The P/E/R Controller handles Block Erase and implements the verify process.
During the Block Erase operation, only the Read Status Register and Reset commands will
be accepted, all other commands will be ignored.
Once the program operation has completed the P/E/R Controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completed successfully, the Write Status Bit
SR0 is ‘0’, otherwise it is set to ‘1’.
5 Add cycles
One bus cycle is required to setup the Block Erase command. Only addresses A19 to
A30 are used, the other address inputs are ignored.
Three bus cycles are then required to load the address of the block to be erased. Refer
to
One bus cycle is required to issue the Block Erase confirm command to start the P/E/R
Controller.
Address
Inputs
Col Add 1,2
Table 7
for the block addresses of each device.
Main Area
Data Intput
Spare
Code
Area
Cmd
85h
2 Add cycles
Address
Col Add 1,2
Inputs
Data Input
Figure
(Program Busy time)
tBLBH2
Confirm
Code
10:
10h
Main Area
Busy
Read Status Register
6 Device operations
70h
Spare
Area
SR0
ai08664
23/51