CY14E064L CYPRESS [Cypress Semiconductor], CY14E064L Datasheet - Page 2

• Manufacturer Part Number: CY14E064L
• Description: 64-Kbit (8K x 8) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 001-06543 Rev. *C
Pin Configurations
Pin Definitions
Pin Name
DQ0-DQ7 Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation.
A
V
HSB
0
V
V
WE
CE
OE
–A
CAP
SS
CC
12
Power Supply Power Supply inputs to the device.
Power Supply Autostore
Input/Output Hardware Store Busy. When low this output indicates a Hardware Store is in progress. When pulled
I/O Type
Ground
Input
Input
Input
Input
V
DQ2
DQ0
Address Inputs used to select one of the 8,192 bytes of the nvSRAM.
Write Enable Input, active LOW. When selected LOW, enables data on the I/O pins to be written to
the address location latched by the falling edge of CE.
Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tri-state.
Ground for the device. Should be connected to ground of the system.
low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull-up resistor
keeps this pin high if not connected. (Connection Optional)
nonvolatile elements.
DQ1
V
A
CAP
A
A
A
A
A
A
A
A
SS
12
2
7
6
5
4
3
1
0
12
10
11
13
4
14
1
2
3
5
6
8
®
7
9
Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
PRELIMINARY
28-SOIC
(Not To Scale)
Top View
Description
OE
DQ5
DQ3
V
HSB
A
CE
DQ7
DQ6
DQ4
WE
A
A
A
8
CC
9
11
10
CY14E064L
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