AT45DB021D ATMEL [ATMEL Corporation], AT45DB021D Datasheet
AT45DB021D
Available stocks
Related parts for AT45DB021D
AT45DB021D Summary of contents
Page 1
... Green (Pb/Halide-free/RoHS Compliant) Packaging Options 1. Description The AT45DB021D is a 2.7V, serial-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The AT45DB021D supports RapidS serial interface for applications requiring very high speed operations. RapidS serial interface is SPI compatible for frequencies MHz ...
Page 2
... To allow for simple in-system reprogrammability, the AT45DB021D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB021D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
Page 3
... The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND. 3. Block Diagram WP PAGE (256/264 BYTES) BUFFER (256/264 BYTES) SCK CS RESET VCC GND 3638B–DFLASH–02/07 Figure 2- GND 6 VCC 5 WP FLASH MEMORY ARRAY I/O INTERFACE SI AT45DB021D [Preliminary] (1) MLF Top View SCK GND 2 7 RESET VCC ...
Page 4
... Memory Array To provide optimal flexibility, the memory array of the AT45DB021D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus- trates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis ...
Page 5
... A0) and a dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin. 3638B–DFLASH–02/07 specification. The Continuous Array Read bypasses the data buffer and leaves the AT45DB021D [Preliminary] CAR1 . To perform a 5 ...
Page 6
... The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is AT45DB021D [Preliminary] 6 specification. The Continuous Array Read bypasses the data CAR1 ...
Page 7
... A8) that specify the page in the main memory to be written and 8 don’t care bits. When a low-to-high transition occurs on the CS pin, 3638B–DFLASH–02/07 AT45DB021D [Preliminary] SCK . The D1H CAR1 ...
Page 8
... CS pin, the part will erase the selected block of eight pages. The erase operation is internally self-timed and should take place in a maximum time of t this time, the status register will indicate that the part is busy. AT45DB021D [Preliminary During this time, the status register will indicate that the part is busy. ...
Page 9
... SE AT45DB021D [Preliminary] PA2/ PA1/ PA0/ A10 • • • • • • • • • ...
Page 10
... Only those sectors that are not protected or locked down will be erased. The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes. Command Chip Erase Figure 7-1. AT45DB021D [Preliminary] 10 PA5/ PA4/ PA3/ A14 A13 ...
Page 11
... Sector Protection Register. The status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be deter- mined by checking the Status Register. 3638B–DFLASH–02/07 AT45DB021D [Preliminary] 11 ...
Page 12
... Disable Sector Protection commands. If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector pro- tection is desired and if the WP pin is not used. AT45DB021D [Preliminary] 12 Byte 1 3DH Enable Sector Protection ...
Page 13
... WPE 2 Disable Sector Command Protection Command – Issue Command Issue Command X Not Issued Yet or 2 Issue Command – Issue Command AT45DB021D [Preliminary] , then the content of the Sector CC time) as long as the Enable Sec- WPD 3 Sector Protection Status X Disabled Disabled – Enabled X Enabled ...
Page 14
... Sector Protection Register. Table 9-2. Sector Number Protected Unprotected Table 9-3. Sectors 0a, 0b Unprotected Protect Sector 0a Protect Sector 0b (Page 8-127) Protect Sectors 0a (Page 0-7), 0b (Page 8-127) Note: AT45DB021D [Preliminary] 14 Sector Protection Register Sector 0 (0a, 0b) 0a (Page 0-7) Bit (1) 1. The default value for bytes 0 through 7 when shipped from Atmel x = don’ ...
Page 15
... Sector Protection Register and before the register can be reprogrammed, then the erroneous program or erase command will not be processed because all sectors would be protected. Command Erase Sector Protection Register Figure 9-2. 3638B–DFLASH–02/07 AT45DB021D [Preliminary] Byte 1 3DH Erase Sector Protection Register CS Opcode Opcode ...
Page 16
... Command Program Sector Protection Register Figure 9-3. Program Sector Protection Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB021D [Preliminary during which time the Status Register will indicate that the device is busy Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte 4 Section 9 ...
Page 17
... Dummy Byte Read Sector Protection Register Opcode X X Each transition represents 8 bits AT45DB021D [Preliminary] Byte 1 Byte 2 Byte 3 32H xxH xxH X Data Byte Data Byte ...
Page 18
... Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure 10-1. Sector Lockdown CS SI AT45DB021D [Preliminary] 18 Byte 1 3DH Opcode Opcode Opcode Byte 1 ...
Page 19
... Sector 0 (0a, 0b) (Page 0-7) Bit 7, 6 details the values read from the Sector Lockdown Register. Sector Lockdown Register xx = Dummy Byte Data Byte AT45DB021D [Preliminary] 0 (0a, 0b) See Below 0a 0b (Page 8-127) Bit 5, 4 Bit ...
Page 20
... Therefore, the contents of the buffer will be altered from its previous state when this command is issued. Figure 10-3. Program Security Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB021D [Preliminary] 20 Security Register • • • One-time User Programmable , during which time the Status Register will indicate that the device is busy. If the device P ...
Page 21
... SCK pin to load the opcode and the address bytes from the input pin (SI). On the low-to-high transition of the CS pin, the data bytes in the selected main memory page will be compared with 3638B–DFLASH–02/07 Opcode X X Each transition represents 8 bits AT45DB021D [Preliminary] X Data Byte Data Byte the status register can be monitored to deter- XFR ...
Page 22
... Erase, Block Erase, Sector Erase, Chip Erase and Auto Page Rewrite. The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit then the data in the main memory page matches the AT45DB021D [Preliminary] 22 Figure 25-1 (page 45) is recommended ...
Page 23
... The device density is indicated using bits and 2 of the status register. For the AT45DB021D, the four bits are 0111 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
Page 24
... RDPD down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure 12-2. Resume from Deep Power-Down AT45DB021D [Preliminary] 24 time. Once the device has entered the Deep Power-down mode, all instructions EDPD CS SI Each transition represents 8 bits time before the device can receive any commands ...
Page 25
... Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. 3638B–DFLASH–02/07 AT45DB021D [Preliminary] , during which time the Status Register will indicate that the device is P Byte 1 ...
Page 26
... Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte. AT45DB021D [Preliminary] 26 Bit 3 ...
Page 27
... Group C can be executed. During the internally self- timed portion of Group B commands 5 through 10, only Group C commands 3 and 4 can be exe- cuted. Finally, during the internally self-timed portion of a Group D command, only the Status Register Read command should be executed. 3638B–DFLASH–02/07 AT45DB021D [Preliminary] 27 ...
Page 28
... Buffer to Main Memory Page Program with Built-in Erase Buffer to Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program through Buffer AT45DB021D [Preliminary] 28 Read Commands Program and Erase Commands Opcode D2H E8H ...
Page 29
... Note: 3638B–DFLASH–02/07 Protection and Security Commands Additional Commands (1) Legacy Commands 1. These legacy commands are not recommended for new designs. AT45DB021D [Preliminary] Opcode 3DH + 2AH + 7FH + A9H 3DH + 2AH + 7FH + 9AH 3DH + 2AH + 7FH + CFH 3DH + 2AH + 7FH + FCH 32H ...
Page 30
... D7h E8h Note Don’t Care AT45DB021D [Preliminary] 30 Address Byte Address Byte ...
Page 31
... N AT45DB021D [Preliminary] Address Byte ...
Page 32
... The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. AT45DB021D [Preliminary During power-up, the internal Power-on Reset circuitry keeps the device in ...
Page 33
... I during a buffer read maximum @ 20 MHz. CC1 2. All inputs are 5 volts tolerant. 3638B–DFLASH–02/07 AT45DB021D [Preliminary] *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and ...
Page 34
... Page Erase Time (256/264 bytes Block Erase Time (2,048/2,112 bytes Sector Erase Time (32,768/33,792 bytes Chip Erase Time CE t RESET Pulse Width RST t RESET Recovery Time REC AT45DB021D [Preliminary] 34 Min Typ Max Units 66 MHz 66 MHz 33 MHz 6.8 ns 6.8 ns 0.1 V/ns 0 ...
Page 35
... MHz) of the RapidS serial case. 3638B–DFLASH–02/07 2.4V AC DRIVING 1.5V LEVELS 0.45V DEVICE UNDER TEST 30 pF period. These timing waveforms are valid over the full frequency range (max- WL AT45DB021D [Preliminary] AC MEASUREMENT LEVEL page 36. Waveform 1 shows the SCK signal being ). Timing waveforms 1 and 2 conform ...
Page 36
... Waveform 2 – SPI Mode 3 Compatible (for Frequencies MHz) CS SCK HIGH 21.3 Waveform 3 – RapidS Mode SCK HIGH IMPEDANCE SO SI 21.4 Waveform 4 – RapidS Mode SCK HIGH AT45DB021D [Preliminary CSS VALID OUT VALID ...
Page 37
... Last bit of BYTE-MOSI is clocked out from the Master. E. Last bit of BYTE-MOSI is clocked into the slave. F. Slave clocks out first bit of BYTE-SO. G. Master clocks in first bit of BYTE-SO. H. Slave clocks out second bit of BYTE-SO. I. Master clocks in last bit of BYTE-SO. 3638B–DFLASH–02/07 AT45DB021D [Preliminary ...
Page 38
... SI (INPUT) MSB Don’t Care 21.8 Command Sequence for Read/Write Operations for Page Size 264 Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB AT45DB021D [Preliminary] 38 CMD 8 bits 8 bits Page Address Bits ...
Page 39
... CS SI (INPUT) CMD 22.2 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page (INPUT) Each transition represents 8 bits 3638B–DFLASH–02/07 AT45DB021D [Preliminary] FLASH MEMORY ARRAY BUFFER TO MAIN MEMORY PAGE PROGRAM BUFFER (256/264 BYTES) BUFFER WRITE I/O INTERFACE SI BINARY PAGE SIZE ...
Page 40
... Main Memory Page Read CS SI (INPUT) CMD SO (OUTPUT) 23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer (INPUT) SO (OUTPUT) AT45DB021D [Preliminary] 40 FLASH MEMORY ARRAY MAIN MEMORY READ PAGE READ I/O INTERFACE SO ADDRESS FOR BINARY PAGE SIZE A15-A8 A17-A16 ...
Page 41
... A X MSB MSB ADDRESS BITS A17 - MSB MSB AT45DB021D [Preliminary] 1 Dummy Byte BFA7 DATA BYTE MSB BIT 2047/2111 ...
Page 42
... MSB HIGH-IMPEDANCE SO 24.5 Buffer Read (Opcode D4H SCK OPCODE MSB HIGH-IMPEDANCE SO AT45DB021D [Preliminary OPCODE ADDRESS BITS A17- MSB ...
Page 43
... MSB OPCODE DON'T CARE MSB AT45DB021D [Preliminary DATA BYTE MSB MSB ...
Page 44
... CS 0 SCK MSB HIGH-IMPEDANCE SO 24.10 Status Register Read (Opcode D7H SCK SI 1 MSB HIGH-IMPEDANCE SO 24.11 Manufacturer and Device Read (Opcode 9FH) CS SCK SI HIGH-IMPEDANCE SO Note: Each transition AT45DB021D [Preliminary OPCODE DON'T CARE ...
Page 45
... The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 3638B–DFLASH–02/07 START provide address (82H) END AT45DB021D [Preliminary] and data BUFFER WRITE (84H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H) ...
Page 46
... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. AT45DB021D [Preliminary] 46 START ...
Page 47
... Very Thin Micro Lead-frame Package (MLF) 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.209” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 3638B–DFLASH–02/07 AT45DB021D [Preliminary] Ordering Code Package AT45DB021D-MU 8M1-A AT45DB021D-SSU ...
Page 48
... Packaging Information 27.1 8M1-A – MLF BOTTOM VIEW 2325 Orchard Parkway San Jose, CA 95131 R AT45DB021D [Preliminary Pin 1 ID TOP VIEW A2 A 0.45 D2 Pin #1 Notch (0. TITLE 8M1-A, 8-pad 1.00 mm Body, Very Thin Dual Flat Package No Lead (MLF) SIDE VIEW ...
Page 49
... TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R 3638B–DFLASH–02/07 AT45DB021D [Preliminary TITLE 8S1, 8-lead (0.150" ...
Page 50
... It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. 5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB021D [Preliminary TOP VIEW ...
Page 51
... Revision History Revision Level – Release Date A – June 2006 B – February 2007 3638B–DFLASH–02/07 AT45DB021D [Preliminary] History Initial Release Removed RDY/BUSY pin references. 51 ...
Page 52
... Atmel Corporation. All rights reserved. Atmel ® registered trademarks, RapidS and others are trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers ...