IS41LV16257 ISSI [Integrated Silicon Solution, Inc], IS41LV16257 Datasheet - Page 4

• Manufacturer Part Number: IS41LV16257
• Description: 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
• Manufacturer: ISSI [Integrated Silicon Solution, Inc]

IS41C16257
IS41LV16257
FUNCTIONAL DESCRIPTION
The IS41C16257 and the IS41LV16257 are CMOS DRAMs
optimized for high-speed bandwidth, low-power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are entered
nine bits (A0-A8) at a time. The row address is latched by
the Row Address Strobe (
latched by the Column Address Strobe (
to latch the first nine bits and
nine bits.
The IS41C16257 and the IS41LV16257 has two
controls,
internally generate a
manner to the single
DRAMs. The key difference is that each
corresponding I/O tristate logic (in conjunction with
WE
controls I/O8 - I/O15.
The IS41C16257 and the IS41LV16257
determined by the first
LOW and the last transitioning back HIGH. The two
controls give the IS41C16257 both BYTE READ and BYTE
WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bringing
terminated by returning both
ensure proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum t
must not be initiated until the minimum precharge time t
t
Read Cycle
A read cycle is initiated by the falling edge of
whichever occurs last, while holding
address must be held for a minimum time specified by t
Data Out becomes valid only when t
are all satisfied. As a result, the access time is dependent
4
CP
has elapsed.
and
RAS
LCAS
).
LCAS
and
UCAS
CAS
CAS
controls
RAS
CAS
signal functioning in an identical
time has expired. A new cycle
. The
RAS
input on the other 256K x 16
(
CAS
LCAS
RAS
). The column address is
LCAS
is used to latch the latter
I/O0 - I/O7 and
or
WE
RAC
and
UCAS
RAS
CAS
HIGH. The column
, t
and
CAS
AA
CAS
CAS
, t
).
) transitioning
LOW and it is
UCAS
CAC
RAS
CAS
controls its
function is
HIGH. To
and t
OE
is used
or
UCAS
inputs
CAS
CAS
and
OE
OEA
RP
AR
,
,
.
on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of
whichever occurs last. The input data must be valid at or
before the falling edge of
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory:
1. By clocking each of the 512 row addresses (A0 through
2. Using a
CAS
or device selection is allowed. Thus, the output remains in
the High-Z state during the cycle.
Power-On
After application of the V
200 s is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a
During power-on, it is recommended that
or be held at a valid V
A8) with
read-modify-write or
dressed row.
RAS
holding
internal 9-bit counter provides the row addresses and the
external address inputs are ignored.
Integrated Silicon Solution, Inc. — 1-800-379-4774
-before-
refresh is activated by the falling edge of
CAS
RAS
CAS
RAS
LOW. In
at least once every 8 ms. Any read, write,
-before-
is a refresh-only mode and no data access
IH
RAS
CAS
to avoid current surges.
CAS
RAS
CC
-only cycle refreshes the ad-
-before-
or
refresh cycle.
supply, an initial pause of
WE
, whichever occurs last.
RAS
RAS
refresh cycle, an
ISSI
CAS
track with V
CAS
RAS
RAS
and
-before-
DR004-1B
signal).
, while
05/24/99
WE
CC
®
,