STK11C48-N25 SIMTEK [Simtek Corporation], STK11C48-N25 Datasheet - Page 8

• Manufacturer Part Number: STK11C48-N25
• Manufacturer: SIMTEK [Simtek Corporation]

STK11C48
March 2006
Internally,
the
tile information is transferred into the
After the t
be ready for
RECALL
Nonvolatile Element cells. The nonvolatile data can
be recalled an unlimited number of times.
POWER-UP RECALL
During power up, or after any low-power condition
(V
latched. When V
voltage of V
be initiated and will take t
If the STK11C48 is in a
power-up
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
CC
CC
SRAM
or between E and system V
< V
100
80
60
40
20
0
operation in no way alters the data in the
RESET
RECALL
RECALL
data is cleared, and second, the nonvola-
RECALL
SWITCH
Figure 2: I
), an internal
READ
cycle time the
, a
CC
50
, the
is a two-step procedure. First,
once again exceeds the sense
RECALL
and
SRAM
CC
Cycle Time (ns)
100
WRITE
RESTORE
(max) Reads
WRITE
RECALL
cycle will automatically
data will be corrupted.
SRAM
150
CC
to complete.
state at the end of
.
TTL
CMOS
operations. The
request will be
will once again
200
SRAM
cells.
HARDWARE PROTECT
The STK11C48 offers hardware protection against
inadvertent
conditions. When V
operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C48 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between I
time. Worst-case current consumption is shown for
both
perature range, V
chip enable). Figure 3 shows the same relationship
for
less than 100%, only standby current is drawn
when the chip is disabled. The overall average cur-
rent drawn by the STK11C48 depends on the fol-
lowing items: 1)
duty cycle of chip enable; 3) the overall cycle rate
for accesses; 4) the ratio of
the operating temperature; 6) the V
O loading.
8Document Control # ML0003 rev 0.2
WRITE
CMOS
100
80
60
40
20
0
cycles. If the chip enable duty cycle is
and
STORE
Figure 3: I
TTL
CMOS
50
CC
CC
operation during low-voltage
input levels (commercial tem-
= 5.5V, 100% duty cycle on
< V
Cycle Time (ns)
CC
vs.
100
SWITCH
(max) Writes
TTL
READ
, all software
150
input levels; 2) the
CC
TTL
CMOS
cc
s to
and
level; and 7) I/
200
READ
WRITE
STORE
cycle
s; 5)