STK11C88_08 SIMTEK [Simtek Corporation], STK11C88_08 Datasheet - Page 4

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STK11C88_08

Manufacturer Part Number
STK11C88_08
Description
32Kx8 SoftStore nvSRAM
Manufacturer
SIMTEK [Simtek Corporation]
Datasheet
STK11C88
Document Control #ML0012 Rev 2.0
SRAM READ CYCLES #1 & #2
Note f:
Note g: I/O state assumes E, G < V
Note h: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
SRAM READ CYCLE #2: E and G Controlled
DQ (DATA OUT)
NO.
10
11
1
2
3
4
5
6
7
8
9
DQ (D ATA OUT)
ADDRESS
27
Jan, 2008
ADDR ESS
W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
t
t
t
t
t
t
t
t
t
t
t
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
#1, #2
f
I
,
g
g
h
h
CC
t
G
SYMBOLS
E
ELEH
e
d, e
f
t
t
t
t
t
t
t
t
t
t
t
ACS
RC
AA
OE
OH
LZ
HZ
OLZ
OHZ
PA
PS
Alt.
IL
and W > V
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to Output Active
Address Change or Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
ST AND BY
t
ELI CC H
t
IH
t
ELQ X
1 0
AXQX
t
6
t
; device is continuously selected.
AV QV
5
G L Q X
3
8
t
G L QV
4
PARAMETER
t
t
EL Q V
E LE H
t
1
AVQV
2
AC T IVE
3
t
4
AVAV
2
f
f, g
DATA VALID
t
EHAX
29
DAT A VAL ID
STK11C88-25
MIN
25
5
5
0
0
(V
t
GH Q Z
9
CC
MAX
25
25
10
10
10
25
t
EHQ Z
7
t
= 5.0V + 10%)
EHI CC L
11
STK11C88-45
MIN
45
5
5
0
0
MAX
45
45
20
15
15
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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