HT62L256-28SOP-A HOLTEK [Holtek Semiconductor Inc], HT62L256-28SOP-A Datasheet

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HT62L256-28SOP-A

Manufacturer Part Number
HT62L256-28SOP-A
Description
CMOS 32Kx8 Low Power SRAM
Manufacturer
HOLTEK [Holtek Semiconductor Inc]
Datasheet
Preliminary
Features
General Description
The HT62L256 is a 262,144-bit static random access
memory organized into 32,768 words by 8 bits and oper-
ating from a low power range of 2.7V to 3.3V supply volt-
age. It is fabricated with high performance CMOS
process that provides both high speed and low power
feature with typical standby current of 2 A and maxi-
mum access time of 70ns.
Block Diagram
Pin Assignment
Rev. 0.00
Operation voltage: 2.7V~3.3V
Low power consumption:
High speed access time: 70ns
Input levels are LVTTL-compatible
Operating current: 20mA max.
Standby current: 2 A
CMOS 32K´8 Low Power SRAM
1
The HT62L256 has an automatic power down feature,
reducing the power consumption significantly when chip
is deselected. The HT62L256 supports the JEDEC
standard 28-pin SOP and TSOP package.
Automatic power down when chip is deselected
Three state outputs
Fully static operation
Data retention supply voltage as low as 2.0V
Easy expansion with CS and OE options
28-pin SOP/TSOP package
HT62L256
August 15, 2002

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HT62L256-28SOP-A Summary of contents

Page 1

... Fully static operation Data retention supply voltage as low as 2.0V Easy expansion with CS and OE options 28-pin SOP/TSOP package The HT62L256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The HT62L256 supports the JEDEC standard 28-pin SOP and TSOP package. ...

Page 2

... Min. Typ. 2.7 3.0 0 CS OUT DD V =Max, I =2mA =Min 1mA =0mA IH OUT CS =0mA IH OUT CS V 0.2V HT62L256 = Max. Unit August 15, 2002 ...

Page 3

... When the I/O pins are in data output mode, they should not be forced with inverse signals Rev. 0.00 Preliminary Ta= Min. Typ. Max HT62L256 =3.0V 10% DD Unit August 15, 2002 ...

Page 4

... See figures below WE Mode X Standby H Output Disable H Read L Write Conditions Min 0. See retention timing See retention timing RC 4 HT62L256 D0~D7 High-Z High-Z Dout Din Ta Max. Unit 3 August 15, 2002 ...

Page 5

... Read cycle 2 address controlled ( Read cycle 3 chip select controlled ( Note high for read cycle 2. Device is continuously enabled, CS=V 3. Address is valid prior to or coincident with the CS transition low 4. OE Transition is measured at 500mV from the steady state Rev. 0.00 Preliminary IL 5 HT62L256 August 15, 2002 ...

Page 6

... Write cycle 1 OE clock (1) Write cycle 2 OE=V Fixed ( Rev. 0.00 Preliminary 6 HT62L256 August 15, 2002 ...

Page 7

... low during this period, then the I/O pins are in the output state and the data input signals of the opposite phase to the outputs should not be applied 10. Transition is measured at 500mV from the steady state Rev. 0.00 Preliminary ) of a low CS and a low HT62L256 August 15, 2002 ...

Page 8

... Package Information 28-pin SOP (330mil) outline dimensions Symbol Min. A 453 B 326 700 Rev. 0.00 Preliminary Dimensions in mil Nom HT62L256 Max. 477 336 20 728 104 August 15, 2002 ...

Page 9

... TSOP (8´13.4) outline dimensions Symbol Min 0. 11.70 H 13. 7. Rev. 0.00 Preliminary Dimensions in mm Nom. 0.20 0.55 0.50 0.8 9 HT62L256 Max. 1.25 0.18 1.05 11.90 13.60 8.10 5 August 15, 2002 ...

Page 10

... Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 0.00 Preliminary 10 HT62L256 August 15, 2002 ...

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